Principal Design Engineer – High-Speed Interconnect

Arm; Austin (TX); Hybrid; USD 249,900 - 338,100; Full time

Job summary

Arm seeks a seasoned silicon engineer to own microarchitecture, RTL development, and integration of high-speed interconnect subsystems across multiple silicon products. You will translate system requirements into detailed RTL, interfaces, and register definitions, ensuring timely delivery.

You will drive the development process from concept to synthesis, collaborating with architecture, verification, performance, firmware, physical design, and implementation teams to meet bandwidth, latency,

Qualifications

• 8+ years in RTL, microarchitecture, or related semiconductor roles.
• Deep hands-on SystemVerilog for high-performance subsystems.
• Expertise in PCIe, CXL, UALink including transaction flows and memory connectivity.
• Experience with coherent/non-coherent interconnects and memory systems.
• Strong knowledge of AXI, CHI, ACE, APB, and streaming interfaces.
• Experience with CDC, RDC, reset sequencing, lint, formal verification, timing, and waveform debugging.
• Ability to translate architecture into microarchitecture docs and RTL.
• Proven leadership and cross-functional delivery.
• Bachelor’s or Master’s degree in EE/CE/CS or related.

Responsibilities

• Own microarchitecture, RTL development, and integration of high-speed interconnect subsystems.
• Translate requirements into microarchitecture specs, interfaces, register definitions, and RTL.
• Drive development from concept through RTL, integration, verification, and delivery.
• Collaborate with architecture, verification, performance, firmware, and design teams to meet targets.
• Analyze traffic, workloads, and buffer requirements to guide tradeoffs; lead technical reviews.

Skills

RTL design & microarchitecture

SystemVerilog

PCIe/CXL/UALink expertise

Coherent interconnects & memory

AXI/CHI/ACE interfaces

CDC/RDC/verification tooling

Technical leadership & delivery

Education

Bachelor’s or Master’s degree in Electrical/Computer Engineering/CS

Tools

PCIe

CXL

UALink

Synthesis

Formal verification

Job description

Responsibilities

Own the microarchitecture, RTL development, and integration of high-speed interconnect subsystems, including PCIe, CXL, and UALink, across multiple silicon products. Translate system and protocol requirements into implementation-ready microarchitecture specifications, interfaces, register definitions, and synthesizable RTL, ensuring detailed execution and delivery.

Responsibilities

Own the microarchitecture, RTL development, and integration of high-speed interconnect subsystems, including PCIe, CXL, and UALink, across multiple silicon products. Translate system and protocol requirements into implementation-ready microarchitecture specifications, interfaces, register definitions, and synthesizable RTL, ensuring detailed execution and delivery.

Drive the development process from concept through RTL creation, subsystem integration, verification support, synthesis preparation, and final delivery. Collaborate with architecture, verification, performance, firmware, physical design, and implementation teams to meet functionality, bandwidth, latency, power, area, and timing targets, encouraging a culture of inclusion and teamwork.

Analyze traffic patterns, workloads, queue depths, credits, outstanding transactions, and buffer requirements to guide implementation tradeoffs. Lead technical reviews, debug cross-functional issues, improve building methodologies, and mentor engineers, ensuring outstanding performance and reliability.

Required Skills And Experience

• 8+ years of experience in RTL build, microarchitecture, subsystem integration, or related semiconductor roles.
• Deep hands-on expertise in SystemVerilog and the development of sophisticated, high-performance digital subsystems.
• Deep understanding of PCIe, CXL, and UALink, covering transaction flows, ordering, flow control, retries, error handling, host/device integration, memory expansion, and coherent connectivity.
• Experience with coherent or non-coherent interconnects, cache hierarchies, memory systems, and high-speed I/O subsystems.
• Strong understanding of AXI, CHI, ACE, APB, streaming interfaces, buffering, arbitration, scheduling, and backpressure.
• Experience with CDC, RDC, reset sequencing, low-power build, lint, X-propagation, formal verification, synthesis, timing analysis, and waveform debug.
• Ability to convert architectural requirements into clear microarchitecture documents and high-quality RTL.
• Proven technical leadership, communication, and delivery skills across multi-functional teams.
• Bachelor’s or Master’s degree, or equivalent experience, in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

Nice to Have Skills and Experience

• Experience with PCIe Gen6 or later, CXL 2.0 or later, UALink, chiplets, or die-to-die connectivity.
• Knowledge of RAS, IDE, TDISP, security, memory pooling, CXL.cache, CXL.mem, and accelerator connectivity.
• Experience integrating third-party IP, PHYs, firmware-visible capabilities, PCIe configuration space, BARs, interrupts, and error-management features.
• Validated experience in delivering sophisticated RTL or subsystem builds on schedule and meeting functional, performance, power, area, and quality targets.

In Return

When joining our team, you are joining a collaborative environment where leadership is about empowering others. We embrace new and different ideas and perspectives, because we believe the best innovation only happens in a diverse and psychologically safe environment.

We support flexible working and ask our teammates to come into the office at least two days per week for planning, design discussions, and other team activities.

Salary Range

$249,900-$338,100 per year

We value people as individuals and our dedication is to reward people competitively and equitably for the work they do and the skills and experience they bring to Arm. Salary is only one component of Arm's offering. The total reward package will be shared with candidates during the recruitment and selection process.

Accommodations at Arm

At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email [e-mail] . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.

Hybrid Working at Arm

Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.

Equal Opportunities at Arm

Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.