RTL Design Engineer: NoC & High‑Speed Interconnect

Architect Labs; Palo Alto (CA); Presencial; USD 150.000 - 230.000; Jornada completa

Descripción de la vacante

Architect Labs is seeking a seasoned RTL Design Engineer to own the AI-driven interconnect fabric for production silicon. You will define block-level microarchitecture, drive high-speed NoC design, and implement AMBA-based interconnects, ensuring low latency and high bandwidth for ML workloads.

Collaboration with DV, SW and ML teams is essential for a successful tapeout. You will lead crossbar and NoC topology design, work on PCIe/CXL/UCIe bridges, and support FPGA prototyping on Xilinx

Formación

• Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a closely related field.
• 5+ years in RTL design with at least one advanced-node tapeout experience involving on-chip interconnects, NoC fabrics, or high-speed I/O subsystems.
• Deep familiarity with ARM AMBA protocol suite — AXI4/AXI5, ACE/ACE-Lite, CHI, and AHB/APB.
• Hands-on experience designing or owning crossbar switches, NoC routers, or multi-layer interconnects with QoS and arbitration.
• Strong proficiency in SystemVerilog for synthesizable RTL and design automation scripts.
• Python skills for traffic modeling, NoC configuration scripting, and regression tooling.
• Experience taking an interconnect or fabric block from RTL through synthesis with PD/timing/area closure.

Responsabilidades

• Own the on-chip fabric RTL end-to-end from NoC topology to timing closure.
• Design and implement AMBA-based interconnect fabrics (AXI/CHI crossbars, NIs, protocol converters).
• Architect NoC routers and topologies, including virtual channels and QoS arbitration.
• Develop high-speed I/O fabric bridges and peer-to-peer engines (PCIe/CXL/UCIe).
• Collaborate with principal architect to refine microarchitectural specs and trade-offs.
• Define and maintain interface specifications (AXI4/AXI5, CHI, AXI-Stream).
• Build and maintain RTL infrastructure and in-house AI-driven flow tools.
• Collaborate with DV, SW and ML teams on verification and traffic modeling.
• Support FPGA prototyping on Xilinx for early functional validation.

Conocimientos

RTL design

AMBA protocol

NoC design

High-speed I/O

peer-to-peer DMA

SystemVerilog

SoC methodology

Python

PPA ownership

Fabric interconnect

Educación

Bachelor/Master/PhD in EE/CE

Herramientas

BookSim

Garnet

Vivado

Vitis

Xilinx FPGA prototyping

Descripción del empleo

Architect Labs is seeking a seasoned RTL Design Engineer to own the AI-driven interconnect fabric for production silicon. You will define block-level microarchitecture, drive high-speed NoC design, and implement AMBA-based interconnects, ensuring low latency and high bandwidth for ML workloads.

Collaboration with DV, SW and ML teams is essential for a successful tapeout. You will lead crossbar and NoC topology design, work on PCIe/CXL/UCIe bridges, and support FPGA prototyping on Xilinx