Principal Design Engineer

IC Resources; Irvine (CA); Remote; USD 180,000 - 260,000; Full time

Benefits offered by this job

Annual performance bonus

Stock options

401(k)

Job summary

IC Resources seeks a Principal Hardware Design Engineer for wireless baseband ASIC/FPGA work. You will own micro-architecture, guide RTL development, and drive high-throughput design from architecture to silicon and FPGA delivery.

You will collaborate with algorithm, systems and customer teams, oversee verification, and mentor engineers while occasional travel to Irvine, CA is required for hands-on lab work.

Qualifications

• 10+ years of industry experience delivering ASIC/FPGA products
• Expert level Verilog/SystemVerilog skills
• Proven ability to lead complex, mission-critical designs
• Strong timing closure, power and resource optimization skills
• Experience defining architecture for large designs and mentoring teams
• Excellent technical writing and cross-team communication skills

Responsibilities

• Own micro-architecture for major subsystems and translate requirements into RTL
• Lead architectural trade studies across performance, area, power and resources
• Set RTL design direction across ASIC/FPGA targets and establish standards
• Guide block/system verification environments with the verification team
• Drive deployment and validation on FPGA platforms and system integration
• Mentor senior engineers and act as a design reviewer across projects
• Engage with customers on integration, requirements and roadmap
• Identify and lead improvements to design flows and tooling

Skills

ASIC/FPGA design

Verilog

SystemVerilog

RTL design

Timing closure

Architectural trade studies

Mentoring

Customer collaboration

Design reviews

Digital signal processing

Tools

UVM

AMBA/AXI interconnects

C++/SystemC

Job description

Principal Hardware Design Engineer, Wireless Baseband (ASIC/FPGA)

Location: Remote (U.S.), with occasional travel to the Irvine, CA area

Employment Type: Permanent

Compensation: Competitive base salary, plus performance bonus and equity

About the Company

Our client is a deep tech company building high performance physical layer technology for next generation wireless networks, with a strong focus on satellite communications. Their hardware accelerated signal processing IP delivers major gains in throughput, reliability and power efficiency over software based approaches, and it is already deployed in commercial systems. Customers include mobile operators, semiconductor vendors and aerospace organizations.

The Role

As a Principal Hardware Design Engineer, you will be the technical authority for complex high throughput designs, from early architecture through silicon and FPGA delivery. You will shape how the hardware is built, guide a team of senior engineers, and work directly with algorithm, systems and customer teams to bring cutting edge wireless technology into production on radiation tolerant devices.

Prior signal processing experience is not required. Exceptional ASIC/FPGA engineers with a record of delivering mission critical designs are strongly encouraged to apply.

This role is open to remote candidates anywhere in the U.S., with occasional travel to the Irvine, CA area for hands on time with hardware in the lab.

What You Will Do

• Own the micro architecture for major subsystems, translating algorithm and system requirements into efficient, scalable RTL
• Lead architectural trade studies across performance, area, power and resource usage, and influence algorithm and system decisions early in the design cycle
• Set technical direction for RTL design across ASIC and FPGA targets, including design standards, reviews and best practices
• Guide the development of block and system level verification environments in partnership with the verification team
• Drive deployment and validation of designs on the latest FPGA platforms, and lead system integration and debug
• Mentor and develop senior and mid level engineers, and act as a design reviewer across projects
• Engage with customers and partners on integration, technical requirements and roadmap discussions
• Identify and lead improvements to design flows, tooling, methodology and overall product quality

What You Bring

• U.S. citizenship or permanent residency (Green Card) is required
• 10+ years of industry experience designing and delivering ASIC and/or FPGA products, with a track record of technical leadership on complex programs
• Proven delivery of mission critical designs where reliability and correctness were essential (for example aerospace, defense, medical, automotive safety or carrier grade networking)
• Expert level Verilog and SystemVerilog skills
• Deep expertise in timing closure, resource optimization, power management, synthesis and timing analysis for high throughput designs
• Experience defining architecture for large designs and leading other engineers through implementation
• Strong technical writing skills across architecture and design specifications, user guides and verification plans
• Excellent communication skills and the ability to influence across engineering teams and with customers

Nice to Have

• Experience with multi Gbps data communication, connectivity or baseband processing designs
• Knowledge of 3GPP physical layer and wireless signal processing (channel coding, equalization, channel estimation, beamforming)
• Experience with AMBA/AXI interconnects
• UVM knowledge or hands on UVM experience
• C++ or SystemC for modeling and integration
• High speed interfaces such as PCIe or JESD204
• Python or other scripting languages
• Experience with AMD/Xilinx FPGAs and toolchains, or ASIC backend flows
• Familiarity with agile and waterfall methodologies, requirements capture and traceability
• Prior experience with space or satellite programs

Competitive compensation, annual performance bonus, stock options, 401(k), medical, dental and vision coverage, flexible hours and hybrid working.