Senior FPGA & RF Signal Processing Engineer

Akkar; San Francisco (CA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Equity package

Comprehensive benefits

Job summary

Akkar in San Francisco seeks a hands-on Senior FPGA & RF Signal Processing Engineer to own high-performance signal-processing systems from requirements to flight-ready hardware. You’ll guide architectures, select platforms, and implement DSP and FPGA designs with close collaboration across RF, antenna, and software teams.

Responsibilities include end-to-end FPGA lifecycle, architecture evaluation, DSP chain design, RTL development, verification, and lab bring-up to ensure robust, high-throughput

Qualifications

• 5+ years preferred in FPGA design with end-to-end ownership.
• Must own FPGA design from architecture to verified hardware.
• Deep SystemVerilog/Verilog/VHDL proficiency and fixed-point DSP.
• Strong RF front-end interfacing, ADC/DAC knowledge, and timing closure.
• Experience building automated verification with Python, MATLAB, UVM, or Cocotb.
• Export control requirements must be met (U.S. export control).

Responsibilities

• Lead full lifecycle of FPGA designs including RTL, simulation, synthesis, timing, bring-up, and delivery.
• Evaluate architectures and hardware platforms; perform trade studies.
• Design and implement DSP chains, including up/down conversion and beamforming.
• Write modular RTL and manage CDCs and timing constraints.
• Develop testbenches and verify against reference models using Python or MATLAB.
• Perform lab bring-up and hardware performance correlation.

Skills

End-to-End FPGA ownership

RTL proficiency

DSP fixed-point

RF front-end integration

Verification frameworks

Education

B.S. in Electrical Engineering

Tools

SystemVerilog

Verilog

VHDL

UVM

Cocotb

MATLAB

Python

Job description

We are seeking a hands-on Senior FPGA & RF Signal Processing Engineer to own the development of high-performance signal-processing systems from initial requirements to working hardware and flight/delivery readiness.

In this role, you will evaluate requirements, recommend optimal architectures and processing platforms, and develop the algorithms and FPGA implementations that turn complex RF signals into reliable, high-throughput communication systems. You will work closely with antenna, RF, and software teams to deliver end-to-end hardware solutions.

Key Responsibilities:

• End-to-End Ownership: Lead the complete lifecycle of FPGA designs, architecture, RTL development, simulation, synthesis, timing closure, board bring-up, lab debugging, and final hardware delivery.
• Architecture & Platform Selection: Evaluate hardware requirements and perform trade studies to recommend processing platforms, FPGA/RFSoC devices, and hardware/software partitioning.
• DSP & Signal Processing: Design, model, and implement signal chains including digital up/down conversion, filtering, modulation/demodulation, channelization, synchronization, and beamforming/calibration functions.
• RTL & Constraints: Write clean, modular fixed-point RTL (SystemVerilog, Verilog, or VHDL); manage clock-domain crossings (CDCs), implementation constraints, and timing closure.
• Verification & Integration: Build automated testbenches against reference models using Python, MATLAB, SystemVerilog/UVM, or Cocotb.
• Hardware Bring-up: Perform hands-on laboratory debugging, board bring-up, and performance correlation using standard lab equipment (analyzers, oscilloscopes, generators).

Qualifications & Requirements:

• Experience: 5+ years preferred (candidates with at least 3+ years of exceptionally strong, relevant experience will be considered).
• Must-Have Track Record: Non-negotiable, personal ownership of an FPGA design taken from start to finish—from initial architecture to verified, measured hardware.
• RTL & DSP Proficiency: Deep fluency in SystemVerilog, Verilog, or VHDL, along with practical fixed-point DSP arithmetic and multirate signal processing.
• RF & Converter Interfacing: Solid understanding of sampled-data systems, high-speed ADCs/DACs, clocking distribution, and integrating FPGA logic with RF front-ends.
• Verification: Demonstrated capability in building reference models and automated verification frameworks using Python, MATLAB, SystemVerilog/UVM, or Cocotb.
• Education: B.S. in Electrical Engineering, Computer Engineering, or equivalent practical experience.
• Export Control: Must meet U.S. export control requirements (ITAR / EAR) as a U.S. Person (U.S. Citizen, Permanent Resident/Green Card holder, or protected individual).

Bonus Skills & Preferred Experience:

• Reference Platforms: Hands-on experience with AMD/Xilinx Zynq UltraScale+ RFSoC or Versal AI Core platforms (or comparable established FPGA vendor platforms).
• Standards & Algorithms: Implementation of 5G NR and/or DVB-S2/S2X modem functions, wireless PHY layer algorithms (OFDM, equalization, FEC), or digital beamforming / MIMO / SDR.
• Protocols & Interfaces: Familiarity with high-speed serial links, AXI/AXI-Stream, JESD204, Ethernet, and external memory interfaces.
• ASIC Exposure: Experience taking an FPGA design through to ASIC implementation is a plus.

What We Offer:

• Opportunity to build cutting-edge space and communications hardware from the ground up.
• Highly competitive equity package and comprehensive benefits.