Senior Hardware Design Engineer

IC Resources; United States; Hybride; USD 120 000 - 170 000; Plein temps

Avantages offerts par ce poste

Stock options

401k with company match

Medical and dental coverage

Résumé du poste

IC Resources is expanding its hardware team and seeking Senior Hardware Design Engineers to advance physical-layer technology for next‑gen wireless and satellite systems. Our IP is deployed in live satellite networks today, with demand accelerating as we scale.

Hybrid on the West Coast; remote across the US is welcome. You will tackle RTL design for FPGA/ASIC, build testbenches, and drive designs from concept through verification and optimization in a collaborative, fast-growing environment.

Qualifications

• Deep, hands on RTL design experience (Verilog/SystemVerilog) on complex ASIC or FPGA products.
• Proven track record delivering digital designs in the ASIC/FPGA space, with real strength in optimizing timing and hardware resources for high throughput applications
• Experience with power management, synthesis, and timing closure
• Strong documentation habits, specs, user guides, and verification plans that others can actually work from
• Comfort as a power user of EDA tools for simulation and synthesis
• No space or satellite background required. What matters most is deep RTL design experience and the ability to speak in real detail about a design you took from start to finish, the tradeoffs, the hard parts, and how you solved them.

Responsabilités

• Partner with our Algorithm and System Architecture teams to turn requirements into solid micro architectures ready for RTL implementation
• Build designs for both FPGA and ASIC targets using industry standard methods, including developing your own testbenches
• Bring designs up on the latest FPGA platforms for validation and integration testing
• Work across the entire design lifecycle, from micro architecture through verification, physical implementation, and optimization
• Help shape our engineering practices and design standards as the team continues to grow

Connaissances

RTL design

Verilog/SystemVerilog

ASIC/FPGA

Timing optimization

Power management

Documentation

Design tradeoffs

Testbench development

Outils

EDA tools

Description du poste

Hybrid based on the West Coast, open to remote across the US

We're growing our hardware team and hiring multiple Senior Hardware Design Engineers to work on advanced physical layer technology built for next generation wireless and satellite communications systems. Our IP is already deployed and running in live satellite networks today, and demand is accelerating as we scale.

You'll work on cutting edge, space qualified hardware, delivering both standalone and integrated IP solutions built around advanced signal processing and highly resilient physical layer design.

What you'll do

• Partner with our Algorithm and System Architecture teams to turn requirements into solid micro architectures ready for RTL implementation
• Build designs for both FPGA and ASIC targets using industry standard methods, including developing your own testbenches
• Bring designs up on the latest FPGA platforms for validation and integration testing
• Work across the entire design lifecycle, from micro architecture through verification, physical implementation, and optimization
• Help shape our engineering practices and design standards as the team continues to grow

What we're looking for

• Deep, hands on RTL design experience (Verilog/SystemVerilog) on complex ASIC or FPGA products
• A proven track record delivering digital designs in the ASIC/FPGA space, with real strength in optimizing timing and hardware resources for high throughput applications
• Experience with power management, synthesis, and timing closure
• Strong documentation habits, specs, user guides, and verification plans that others can actually work from
• Comfort as a power user of EDA tools for simulation and synthesis
• No space or satellite background required. What matters most is deep RTL design experience and the ability to speak in real detail about a design you took from start to finish, the tradeoffs, the hard parts, and how you solved them.

Nice to have

• Background in communications signal processing (error correction, equalization, channel estimation, beamforming)
• C++ or SystemC for design modeling
• Experience with high speed interfaces (PCI E, JESD)
• Python or another scripting language
• Familiarity with AMD FPGA toolchains or ASIC backend EDA tools

Compensation and benefits

• Competitive compensation package, plus a company wide performance bonus
• 401k with company match
• Medical and dental coverage
• Stock options