Senior FPGA Engineer

TalentBridge; Chandler (AZ); On-site; USD 120,000 - 180,000; Full time

Job summary

TalentBridge is seeking a Senior FPGA Engineer in Chandler, AZ to lead FPGA SoC design across the complete development flow. You will integrate IP, implement high‑performance RTL, and develop userspace drivers and embedded firmware.

The ideal candidate has hands-on FPGA experience with Quartus or Vivado, strong AXI/AMBA knowledge, and a track record of debugging complex FPGA systems in a satellite communications context.

Qualifications

• Strong digital design experience with FPGA/ASIC SoC development.
• Hands-on FPGA implementation using Quartus or Vivado.
• Experience with AMBA AXI and APB interfaces.
• Experience developing high-throughput AXI-Stream IP.
• Ability to create RTL simulations prior to hardware testing.
• Understanding of STA and SDC constraints.
• Experience in PCB schematic capture and board layout contributions.
• Experience implementing high-speed serial protocols (PCIe, Interlaken, USB3, 10GBASE-R).

Responsibilities

• Design, develop, document, debug, and test FPGA SoC systems and IP integration.
• Develop high-performance FPGA IP in VHDL/SystemVerilog.
• Create userspace drivers for FPGA IP (C++).
• Develop firmware for embedded MCUs (C).
• Collaborate with engineering teams across the lifecycle.
• Support validation and optimization of complex FPGA solutions.

Skills

C

C++

Git

RTL design

FPGA design

Education

Bachelor’s degree in Electrical Engineering or Computer Engineering

Tools

Quartus

Vivado

Job description

Location: Chandler, AZ (Onsite 5 days/week)

Senior FPGA Engineer

Position Summary

We are seeking a Senior FPGA Engineer with experience across the entire design flow for complex FPGAs to lead the design, development, and debugging of FPGA SoC systems supporting advanced satellite communications technologies. This role focuses on advanced IP integration, high-performance RTL development, and userspace driver/firmware development.

Responsibilities

• Design, develop, document, debug, and test FPGA SoC systems, including:
  • IP integration into FPGA projects (synthesis and implementation)
  • High-performance FPGA IP development (VHDL/SystemVerilog)
  • Userspace drivers for FPGA IP (C++)
  • Firmware for embedded microcontrollers (C)
• Collaborate effectively with engineering teams and leadership throughout the development lifecycle.
• Support the design, implementation, validation, and optimization of complex FPGA solutions.

Required Qualifications

• Strong digital design experience with FPGA/ASIC SoC development.
• Hands-on FPGA implementation experience using Client (Altera) Quartus or Xilinx Vivado.
• Experience designing and debugging SoC systems utilizing AMBA AXI and APB interfaces.
• Experience developing high-throughput, pipelined AXI-Stream IP optimized for performance.
• Ability to create RTL simulations to identify and resolve issues prior to hardware testing.
• Strong understanding of Static Timing Analysis (STA) and Synopsis Design Constraints (SDC).
• Experience analyzing timing reports and post-synthesis placement/routing to resolve timing violations.
• Experience contributing to FPGA portions of PCB schematic capture and board layout.
• Experience implementing at least one high-speed serial protocol, such as:
  • PCI Express
  • Interlaken
  • USB SuperSpeed
  • 1000BASE-X / SGMII
  • 10GBASE-R
  • 40GBASE-4
  • 100GBASE-R4
• Experience implementing networking protocols including:
  • Layer 1: IEEE 802.3 Ethernet standards (1G-100G)
  • Layer 2/3: IPv4, IPv6, ARP, ICMP, IGMP, UDP, TCP
  • Layer 4: VITA 49.2, DIFI, and/or eCPRI (highly preferred)
• Proficiency in:
  • C
  • C++
  • Git version control
• Strong Microsoft Office skills.
• Experience supporting cross-functional engineering teams.

Preferred Qualifications

• Knowledge of digital IF standards including VITA 49.2, DIFI, or eCPRI.
• Experience with Embedded Linux, including:
  • Linux Kernel
  • Yocto
  • U-Boot
  • Device Tree
• Familiarity with SATCOM waveforms such as:
  • DVB-S2X
  • 5G NTN (3GPP Release 17/18)
• Understanding of secure communications and Zero Trust architectures.
• Experience with:
  • Partial Reconfiguration (DFX)
  • PCIe CvP
• Active DoD Security Clearance or ability to obtain one.

Education

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.

Experience

• 5+ years of FPGA/ASIC SoC design experience.