FPGA Design Engineer

ApTask; California; Vor Ort; USD 150.000 - 230.000; Vollzeit

Zusammenfassung

ApTask is assisting a leading aerospace client in California to fill a Senior ASIC/FPGA Design role. The team focuses on reusable rocket technology and high-assurance digital ICs used in spaceflight systems.

The candidate will design and verify digital ASICs and FPGAs, develop test benches, perform timing and signoff, and work with cross-functional groups across systems and firmware teams. Strong HDL expertise and a track record in full lifecycle IC projects are required.

Qualifikationen

• 7+ years of experience in ASIC design and implementation.
• Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical discipline.
• Experience with FPGA & ASIC design and HDL programming (VHDL/Verilog/SystemVerilog).

Aufgaben

• Design and develop digital ASICs and FPGAs, and/or mixed-signal ASICs with HDL (VHDL, Verilog, SystemVerilog).
• Develop verification methodologies and test benches for block and system-level verification.
• Create and execute test plans, develop test harnesses, and implement coverage models.
• Conduct timing analysis, noise analysis, and other signoff checks.
• Collaborate with cross-functional teams including systems, firmware, architecture, and product engineering.
• Support lab integration and troubleshooting activities.
• Resolve design issues and drive solutions for timing, congestion, and other implementation challenges.

Kenntnisse

ASIC design

HDL programming

FPGA design

Verification

Timing analysis

Cross-functional collaboration

Python scripting

Ausbildung

Bachelors in Electrical/Computer Engineering

Tools

EDA tools

RTL2GDSII

Jobbeschreibung

The client is a private aerospace manufacturer and spaceflight services company, which aims to make access to space more affordable and reliable through the development of reusable rocket technology. It has several ambitious projects in progress, including its New Shepard suborbital rocket, designed for space tourism and research missions, and the New Glenn orbital launch vehicle, intended to compete with SpaceX's Falcon rockets in the commercial satellite launch market.

The client has also been involved in developing lunar landers and other technologies to support NASA's Artemis program, which aims to return humans to the Moon and eventually establish a sustainable human presence there.

Key Responsibilities:

• Design and develop digital ASICs and FPGAs, and/or mixed-signal ASICs Implement designs using HDL (VHDL, Verilog, and/or SystemVerilog)
• Develop verification methodologies and test benches for block and system-level verification
• Create and execute test plans, develop test harnesses, and implement coverage models
• Conduct timing analysis, noise analysis, and other signoff checks
• Collaborate with cross-functional teams including systems, firmware, architecture, and product engineering
• Support lab integration and troubleshooting activities
• Resolve design issues and drive solutions for timing, congestion, and other implementation challenges

Basic Qualifications:

• 7+ years of experience in ASIC design and implementation
• Bachelor's degree in Electrical Engineering,
• Computer Engineering, or related technical discipline Experience with FPGA & ASIC design Proficiency in HDL programming (VHDL, Verilog, and/or SystemVerilog)

Preferred Skills and Experience:

• Advanced degree (MS/PhD) in Electrical Engineering, Computer Engineering, or related field
• Experience in full ASIC/FPGA lifecycle (architecture, design, simulation, verification, validation, integration & test)
• Experience with Software-Defined Radio Architectures, Client/DAC, and/or DSPs
• Knowledge of DSP and communications systems including spread spectrum, forward error correction, and modulation types (QPSK, QAM, PCM/FM, PAM) Strong object-oriented programming and scripting skills (Python, TCL, Perl)
• Experience with physical design flows and industry-standard EDA tools
• Experience with RTL2GDSII physical design and signoff flows Knowledge of deep sub-micron FinFET and CMOS technologies Experience with DFT/Scan/MBIST/LBIST methodologies Experience mentoring junior engineers
• Experience with Linux development environment
• Experience with design verification and test bench development