Principal CPU Power-Management Verification Engineer

SiFive, Inc.; Town of Texas (WI); On-site; USD 150,000 - 185,000; Full time

Job summary

SiFive, Inc. seeks a Principal Design Verification Engineer to lead CPU-subsystem power-management verification across complex SoC environments.

You will define architecture-aware strategies, drive signoff readiness, and coordinate with architecture, RTL, DV, formal, and performance teams to ensure robust verification outcomes. The role emphasizes DVFS, retention, clock gating, and multi-domain interactions for data-center-grade power management.

Qualifications

• Strong hands-on experience with SystemVerilog-based verification, scalable verification planning, assertions, checkers, coverage strategy, and debug workflows for complex hardware subsystems.
• Proven ability to translate architectural intent into an effective verification strategy and execution plan.

Responsibilities

• Lead verification planning and execution for CPU-subsystem power-management features from unit and block level through subsystem integration and signoff.
• Define verification strategies, test plans, assertions, checkers, coverage models, and closure criteria for complex power-state transitions and clock/reset sequencing.
• Drive verification across multiple bench contexts including CoreIP, PMC unit-level, and broader PM unit and uncore environments.
• Own high-value stress, corner-case, and long-run scenarios that expose failures in power-state sequencing, asynchronous clock relationships, retention recovery, reset interactions, wakeup behavior, and activity-monitor correctness.
• Partner with architecture, RTL, DV, and infrastructure teams to review specifications and improve debugability and verification completeness.
• Apply the right verification method for the problem, including simulation, formal techniques, power-aware verification, and emulation where appropriate for subsystem-level signoff.
• Contribute reusable methodology, automation, and verification infrastructure to improve quality and productivity across the broader power-management DV organization.
• Mentor engineers and provide technical leadership across the power-management verification area.

Skills

SystemVerilog

Verification planning

Assertions

Coverage models

Python scripting

Debug workflows

Education

BS/MS/PhD in EE/CE/CS

Tools

Formal verification tools

Emulation platforms

Simulation frameworks

Job description

SiFive, Inc. seeks a Principal Design Verification Engineer to lead CPU-subsystem power-management verification across complex SoC environments.

You will define architecture-aware strategies, drive signoff readiness, and coordinate with architecture, RTL, DV, formal, and performance teams to ensure robust verification outcomes. The role emphasizes DVFS, retention, clock gating, and multi-domain interactions for data-center-grade power management.