Senior Design Verification Architect - CPU Power Management

SiFive, Inc.; Austin (TX); On-site; USD 180,000 - 260,000; Full time

Job summary

SiFive, Inc. is seeking a Principal Design Verification Engineer to lead verification of CPU-subsystem power-management functionality across complex SoC environments.

The role focuses on data‑center‑grade quality, resiliency, and sign‑off readiness. The position requires architecture-aware verification strategies, early risk identification, and collaboration with architecture, RTL, DV, and infrastructure teams to raise the quality bar across the broader PM verification effort.

Qualifications

• Minimum: BS/MS/PhD in Electrical/Computer Engineering or related field.
• 12+ years of CPU/subsystem verification experience; principal-level depth.
• Proven CPU-subsystem power-management verification experience incl. clock/reset, retention, multi-domain.
• Strong SystemVerilog-based verification, coverage, and debug skills.
• Solid scripting and automation in Python or similar.

Responsibilities

• Lead verification planning and execution for CPU-subsystem power-management features from unit and block level through subsystem integration and sign-off.
• Define verification strategies, test plans, assertions, checkers, coverage models, and closure criteria for complex power-state transitions, clock/reset sequencing, retention behavior, DVFS scenarios, warm-reset flows, and multi-domain interactions.
• Drive verification across multiple bench contexts, including CoreIP, PMC unit-level, and broader PM unit and uncore environments.
• Own high-value stress, corner-case, and long-run scenarios that expose failures in power-state sequencing, asynchronous clock relationships, retention recovery, reset interactions, wakeup behavior, and activity-monitor correctness.
• Partner closely with architecture, RTL, DV, and infrastructure teams to review specifications, reduce ambiguity early, and improve debug-ability and verification completeness before issues harden late in the program.
• Drive efficient failure analysis and root‑cause debug across specification, RTL, verification infrastructure, assertions, and stimulus.
• Apply the right verification method for the problem, including simulation, formal techniques, power-aware verification, and emulation as appropriate for subsystem‑level sign-off.
• Contribute reusable methodology, automation, and verification infrastructure that improve quality and productivity across the broader power‑management DV organization.
• Mentor engineers and provide technical leadership across the power‑management verification area, especially for difficult subsystem‑level debug and closure challenges.
• Help define sign‑off expectations suitable for data‑center‑grade CPU subsystems, with attention to correctness across power states, reset behaviors, retention flows, and integration boundaries.

Skills

SystemVerilog

Python scripting

Root-cause analysis

Leadership

Cross-functional collaboration

Education

MS/PhD in Electrical Engineering or related field

Tools

UVM

Ver emulation

Job description

SiFive, Inc. is seeking a Principal Design Verification Engineer to lead verification of CPU-subsystem power-management functionality across complex SoC environments.

The role focuses on data‑center‑grade quality, resiliency, and sign‑off readiness. The position requires architecture-aware verification strategies, early risk identification, and collaboration with architecture, RTL, DV, and infrastructure teams to raise the quality bar across the broader PM verification effort.