Staff Formal Verification Engineer, CPU Core - Equity

SiFive, Inc.; Town of Texas (WI); Hybrid; USD 140,000 - 190,000; Full time

Benefits offered by this job

Healthcare

Equity

Paid time off

Job summary

SiFive, Inc. seeks a Staff Design Verification Engineer to drive formal verification for high‑performance CPU cores. You will own the verification strategy, build scalable environments, and collaborate with architecture and RTL teams to ensure rigorous proof closure.

The role emphasizes property-driven verification, debugging complex microarchitectural behavior, and mentoring peers in formal methods within a fast-paced CPU development environment.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 7+ years of ASIC/CPU/core or SoC design verification experience.
• Direct experience with CPU/core verification and computer architecture knowledge.
• Strong background in RTL formal verification, assertions, and proof closure.
• Proficiency in scripting for automation (Python, Tcl, or Perl).

Responsibilities

• Own formal verification planning and execution for high-performance out-of-order CPU cores.
• Develop verification plans based on architectural intent and microarchitectural risk.
• Create scalable formal environments, property sets, checkers, harnesses, and proof infrastructure.
• Tackle verification problems like pipeline control, issue/dispatch correctness, and load-store ordering.
• Analyze proof failures, vacuity, and constraints to drive fixes across RTL and properties.
• Mentor engineers on formal-debug practices and methodology.

Skills

CPU verification

Formal verification

Debugging

Proof planning

Python

RTL knowledge

Education

BS in EE/CE/CS

MS in EE/CE/CS

Tools

SystemVerilog

UVM

Job description

SiFive, Inc. seeks a Staff Design Verification Engineer to drive formal verification for high‑performance CPU cores. You will own the verification strategy, build scalable environments, and collaborate with architecture and RTL teams to ensure rigorous proof closure.

The role emphasizes property-driven verification, debugging complex microarchitectural behavior, and mentoring peers in formal methods within a fast-paced CPU development environment.