Staff Formal CPU Core Verification Engineer

SiFive, Inc.; Austin (TX); On-site; USD 140,000 - 190,000; Full time

Benefits offered by this job

Healthcare

Retirement plans

Paid time off

Equity

Job summary

SiFive, Inc. is seeking a Staff Design Verification Engineer to drive formal verification of high‑performance CPU core functionality. This role focuses on applying formal methods to complex out‑of‑order CPU core microarchitecture, owning difficult verification problems and building scalable proof infrastructure.

You will collaborate with architecture, RTL, and DV engineers to ensure high-quality verification and robust signoff across core units and interfaces.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 7+ years of relevant experience in ASIC, CPU/core, or SoC design verification with hands-on ownership of complex problems.
• Direct experience with CPU/core verification and solid understanding of computer architecture.
• Strong hands-on experience with formal verification for RTL, including assertion-based verification, proofs, and closure of non-trivial properties.
• Experience developing assertions and formal strategies for control-heavy, ordering-sensitive hardware.
• Strong debugging skills to root-cause issues across spec, RTL, properties, and infra.
• Familiarity with scripting or programming in Python, Perl, Tcl for automation.

Responsibilities

• Own formal verification planning and execution for high‑performance out-of-order CPU core areas.
• Develop formal verification plans based on architectural intent and risk.
• Create and maintain scalable formal environments, property sets, checkers, and proof infra.
• Target high-value verification problems: pipeline control, issue and dispatch, load-store ordering.
• Use abstraction, decomposition, bounded proofs, and connectivity checks to improve proof convergence.
• Analyze proof failures and drive fixes across RTL, properties, and infra.
• Partner with architecture, RTL, and DV engineers to align results with goals.
• Contribute reusable formal methodology and debugging workflows.
• Mentor other engineers through reviews and best practices.

Skills

ASIC verification

CPU/core verification

Formal verification

Assertion-based verification

Proof analysis

Abstraction techniques

Scripting (Python/Perl/Tcl)

Debugging

Verification methodology

RTL/Architecture collaboration

Signoff discipline

Education

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Job description

SiFive, Inc. is seeking a Staff Design Verification Engineer to drive formal verification of high‑performance CPU core functionality. This role focuses on applying formal methods to complex out‑of‑order CPU core microarchitecture, owning difficult verification problems and building scalable proof infrastructure.

You will collaborate with architecture, RTL, and DV engineers to ensure high-quality verification and robust signoff across core units and interfaces.