Senior CPU Frontend Verification Architect

SiFive, Inc.; Austin (TX); On-site; USD 180,000 - 260,000; Full time

Benefits offered by this job

Healthcare

Retirement plans

Paid time off

Job summary

SiFive, Inc. in Austin, Texas, seeks a Principal Design Verification Engineer to lead verification strategy for the CPU Core Frontend in a high‑performance out‑of‑order core.

You will define architecture‑aware strategies, identify microarchitectural risk early, and drive verification quality across the DV organization. You will mentor engineers, develop test plans and coverage, and coordinate with architects from feature definition through sign‑off, tackling memory management unit verification

Qualifications

• 12+ years in CPU/core or SoC functional verification.
• Direct experience with out‑of‑order CPU core verification.
• Deep expertise in CPU frontend verification (branch prediction and fetch).
• Strong knowledge of verification flow: test plans, stimulus, coverage.

Responsibilities

• Lead verification planning and execution for CPU frontend functionality (branch prediction, fetch).
• Define strategies, test plans, checkers, scoreboards, assertions, and coverage models.
• Drive verification of branch prediction structures and fetch behavior.
• Mentor engineers and shape reusable DV infrastructure and methodologies.
• Collaborate with architects from feature definition to sign‑off for frontend verification.

Skills

Frontend verification

Branch prediction

Instruction fetch

Verification strategy

Scripting fundamentals

Mentoring

Memory-management verification

CPU core verification

Education

BS, MS, or PhD in Electrical Engineering or related field

Tools

Simulation tools

Emulation

Job description

SiFive, Inc. in Austin, Texas, seeks a Principal Design Verification Engineer to lead verification strategy for the CPU Core Frontend in a high‑performance out‑of‑order core.

You will define architecture‑aware strategies, identify microarchitectural risk early, and drive verification quality across the DV organization. You will mentor engineers, develop test plans and coverage, and coordinate with architects from feature definition through sign‑off, tackling memory management unit verification