Lead CPU Power-Management Verification Architect

SiFive; Santa Clara (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

SiFive is seeking a Principal Design Verification Engineer to spearhead CPU-subsystem power-management verification across complex SoC environments, delivering data-center-grade signoff readiness.

You will define architecture-aware verification strategies, drive cross-team collaboration with architecture, RTL, DV, and formal teams, and own risk-driven verification plans to ensure robust power-state transitions and clock/reset behavior.

Qualifications

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
• 12+ years of relevant experience in CPU, subsystem, SoC, or ASIC functional verification.
• Strong experience in CPU-subsystem or SoC power-management verification, including clock/reset behavior, power-state transitions, retention, gating, and multi-domain interactions.
• Strong understanding of high-performance CPU subsystem behavior and verification challenges across core, cluster, cache, and uncore boundaries.
• Strong hands-on experience with SystemVerilog-based verification, scalable verification planning, assertions, checkers, coverage strategy, and debug workflows for complex hardware subsystems.
• Proven ability to translate architectural intent into an effective verification strategy and execution plan.
• Solid software, scripting, and automation skills in Python or similar languages for DV infrastructure and workflow scalability.
• Strong technical communication and cross-functional collaboration skills across architecture, RTL, DV, formal, and performance teams.

Responsibilities

• Lead verification planning and execution for CPU-subsystem power-management features from unit and block level through subsystem integration and signoff.
• Define verification strategies, test plans, assertions, checkers, coverage models, and closure criteria for complex power-state transitions, clock/reset sequencing, retention behavior, DVFS scenarios, warm-reset flows, and multi-domain interactions.
• Drive verification across multiple bench contexts as appropriate, including CoreIP, PMC unit-level, and broader PM unit and uncore environments.
• Own high-value stress, corner-case, and long-run scenarios that expose failures in power-state sequencing, asynchronous clock relationships, retention recovery, reset interactions, wake-up behavior, and activity-monitor correctness.
• Partner closely with architecture, RTL, DV, and infrastructure teams to review specifications, reduce ambiguity early, and improve debugability and verification completeness before issues harden late in the program.
• Drive efficient failure analysis and root-cause debug across specification, RTL, verification infrastructure, assertions, and stimulus.
• Apply the right verification method for the problem, including simulation, formal techniques, power-aware verification, and emulation where appropriate for subsystem-level signoff.
• Contribute reusable methodology, automation, and verification infrastructure that improve quality and productivity across the broader power-management DV organization.
• Mentor engineers and provide technical leadership across the power-management verification area, especially for difficult subsystem-level debug and closure challenges.
• Help define signoff expectations suitable for data-center-grade CPU subsystems, with attention to correctness across power states, reset behaviors, retention flows, and integration boundaries.

Skills

SystemVerilog verification

Python scripting

Verification planning

Debugging

Cross-functional collaboration

Education

EE/CE/CS degree

Tools

Formal verification tools

Emulation platforms

Simulation environments

Job description

SiFive is seeking a Principal Design Verification Engineer to spearhead CPU-subsystem power-management verification across complex SoC environments, delivering data-center-grade signoff readiness.

You will define architecture-aware verification strategies, drive cross-team collaboration with architecture, RTL, DV, and formal teams, and own risk-driven verification plans to ensure robust power-state transitions and clock/reset behavior.