Principal Design Verification Engineer – CPU Subsystem Power Management

SiFive, Inc.; Austin (TX); On-site; USD 180,000 - 260,000; Full time

Job summary

SiFive, Inc. is seeking a Principal Design Verification Engineer to lead verification of CPU-subsystem power-management functionality across complex SoC environments.

The role focuses on data‑center‑grade quality, resiliency, and sign‑off readiness. The position requires architecture-aware verification strategies, early risk identification, and collaboration with architecture, RTL, DV, and infrastructure teams to raise the quality bar across the broader PM verification effort.

Qualifications

• Minimum: BS/MS/PhD in Electrical/Computer Engineering or related field.
• 12+ years of CPU/subsystem verification experience; principal-level depth.
• Proven CPU-subsystem power-management verification experience incl. clock/reset, retention, multi-domain.
• Strong SystemVerilog-based verification, coverage, and debug skills.
• Solid scripting and automation in Python or similar.

Responsibilities

• Lead verification planning and execution for CPU-subsystem power-management features from unit and block level through subsystem integration and sign-off.
• Define verification strategies, test plans, assertions, checkers, coverage models, and closure criteria for complex power-state transitions, clock/reset sequencing, retention behavior, DVFS scenarios, warm-reset flows, and multi-domain interactions.
• Drive verification across multiple bench contexts, including CoreIP, PMC unit-level, and broader PM unit and uncore environments.
• Own high-value stress, corner-case, and long-run scenarios that expose failures in power-state sequencing, asynchronous clock relationships, retention recovery, reset interactions, wakeup behavior, and activity-monitor correctness.
• Partner closely with architecture, RTL, DV, and infrastructure teams to review specifications, reduce ambiguity early, and improve debug-ability and verification completeness before issues harden late in the program.
• Drive efficient failure analysis and root‑cause debug across specification, RTL, verification infrastructure, assertions, and stimulus.
• Apply the right verification method for the problem, including simulation, formal techniques, power-aware verification, and emulation as appropriate for subsystem‑level sign-off.
• Contribute reusable methodology, automation, and verification infrastructure that improve quality and productivity across the broader power‑management DV organization.
• Mentor engineers and provide technical leadership across the power‑management verification area, especially for difficult subsystem‑level debug and closure challenges.
• Help define sign‑off expectations suitable for data‑center‑grade CPU subsystems, with attention to correctness across power states, reset behaviors, retention flows, and integration boundaries.

Skills

SystemVerilog

Python scripting

Root-cause analysis

Leadership

Cross-functional collaboration

Education

MS/PhD in Electrical Engineering or related field

Tools

UVM

Ver emulation

Job description

About the Role

SiFive is searching for a Principal Design Verification Engineer to lead verification of CPU‑subsystem power‑management functionality across complex SoC and subsystem environments. The role focuses on data‑center‑grade quality, resiliency, and sign‑off readiness, and involves defining architecture‑aware verification strategies early, identifying risks, solving subsystem‑level problems, and raising the quality bar across the broader power‑management verification effort.

Responsibilities

• Lead verification planning and execution for CPU‑subsystem power‑management features from unit and block level through subsystem integration and sign‑off.
• Define verification strategies, test plans, assertions, checkers, coverage models, and closure criteria for complex power‑state transitions, clock/reset sequencing, retention behavior, DVFS scenarios, warm‑reset flows, and multi‑domain interactions.
• Drive verification across multiple bench contexts, including CoreIP, PMC unit‑level, and broader PM unit and uncore environments.
• Own high‑value stress, corner‑case, and long‑run scenarios that expose failures in power‑state sequencing, asynchronous clock relationships, retention recovery, reset interactions, wakeup behavior, and activity‑monitor correctness.
• Partner closely with architecture, RTL, DV, and infrastructure teams to review specifications, reduce ambiguity early, and improve debug‑ability and verification completeness before issues harden late in the program.
• Drive efficient failure analysis and root‑cause debug across specification, RTL, verification infrastructure, assertions, and stimulus.
• Apply the right verification method for the problem, including simulation, formal techniques, power‑aware verification, and emulation as appropriate for subsystem‑level sign‑off.
• Contribute reusable methodology, automation, and verification infrastructure that improve quality and productivity across the broader power‑management DV organization.
• Mentor engineers and provide technical leadership across the power‑management verification area, especially for difficult subsystem‑level debug and closure challenges.
• Help define sign‑off expectations suitable for data‑center‑grade CPU subsystems, with attention to correctness across power states, reset behaviors, retention flows, and integration boundaries.

Minimum Qualifications

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 12+ years of relevant experience in CPU, subsystem, SoC, or ASIC functional verification, with depth appropriate for a Principal / T6 role.
• Strong experience in CPU‑subsystem or SoC power‑management verification, including clock/reset behavior, power‑state transitions, retention, gating, and multi‑domain interactions.
• Strong understanding of high‑performance CPU subsystem behavior and the verification challenges that arise across core, cluster, cache, and uncore boundaries.
• Strong hands‑on experience with SystemVerilog‑based verification, scalable verification planning, assertions, checkers, coverage strategy, and debug workflows for complex hardware subsystems.
• Proven ability to translate architectural intent into an effective verification strategy and execution plan.
• Solid software, scripting, and automation skills in Python or similar languages for DV infrastructure and workflow scalability.
• Strong technical communication and cross‑functional collaboration skills across architecture, RTL, DV, formal, and performance teams.

Preferred Qualifications

• Direct experience verifying CPU‑subsystem power‑management features such as DVFS, power gating, retention, warm reset, and clock‑gating behavior across core, cluster, LLC, and uncore domains.
• Experience with PMC‑ or power‑controller‑centric verification, including unit‑level benches and standalone verification flows.
• Experience developing or reviewing checkers for live retention, CCidle, tile or cluster live retention, and related PM correctness checks.
• Experience with formal verification, power‑aware simulation, emulation, or related advanced verification techniques for subsystem‑level sign‑off.
• Experience with subsystem integration issues involving resets, clock‑domain interactions, coherency‑sensitive traffic, and performance‑sensitive power‑state transitions in high‑performance CPU environments.
• Demonstrated ability to influence verification methodology and technical direction beyond immediate ownership.

What Success Looks Like

Verification plans capture the real architectural and integration risks in CPU‑subsystem power management early and clearly. Critical bugs in power‑state transitions, reset sequencing, retention, and clocking behavior are found early, debugged efficiently, and closed with durable fixes. Verification quality improves across power‑management DV through stronger methodology, reusable infrastructure, and better closure discipline. Architecture, RTL, and DV teams rely on this engineer as the technical lead for difficult power‑management verification challenges in data‑center‑grade CPU subsystem development.

Additional Information

Additional compensation may include variable or incentive pay and/or equity. The role is eligible for a comprehensive, competitive benefits package that may include healthcare, retirement plans, paid time off, and more.

Equal Opportunity Employer

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. SiFive is an E‑Verify employer. All applicants will be required to complete a Form I‑9, Employment Eligibility Verification upon hire. We do not use E‑Verify to pre‑screen job candidates and will comply with all E‑Verify regulations.