Lead CPU Subsystem Power-Management Verification Engineer

SiFive; Austin (TX); On-site; USD 180,000 - 240,000; Full time

Job summary

SiFive is seeking a Principal Design Verification Engineer to lead verification of CPU-subsystem power-management functionality across complex SoC environments with data-center-grade quality and signoff readiness.

You will define architecture-aware verification strategy, collaborate with architecture, RTL, formal, and performance teams, and drive reusable methodology and automation for scalable verification across cores, PMC, and uncore domains.

Qualifications

• BS/MS/PhD in EE, CE or CS.
• 12+ years of CPU/subsystem/SoC/ASIC functional verification experience.
• Strong experience in CPU-subsystem power-management verification, including clock/reset, power-state transitions, retention, gating, multi-domain interactions.
• Strong understanding of high-performance CPU subsystem behavior and verification challenges across core, cluster, cache, and uncore boundaries.
• Hands-on SystemVerilog-based verification, scalable planning, assertions, coverage, and debug workflows.

Responsibilities

• Lead verification planning and execution for CPU-subsystem power-management features from unit through signoff.
• Define verification strategies, test plans, assertions, checkers, coverage models, and closure criteria for complex power-state transitions and DVFS scenarios.
• Drive verification across multiple bench contexts (CoreIP, PMC unit-level, and PM unit/un-dedicated environments).
• Own high-value stress, corner-case, and long-run scenarios that expose failures in power-state sequencing, reset interactions, and wake-up behavior.
• Mentor engineers and provide technical leadership across the power-management verification area.

Skills

SystemVerilog

Python scripting

Verification planning

Debugging

Cross-functional

Education

BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science

Tools

SystemVerilog-based verification

Assertions & checkers tooling

Job description

SiFive is seeking a Principal Design Verification Engineer to lead verification of CPU-subsystem power-management functionality across complex SoC environments with data-center-grade quality and signoff readiness.

You will define architecture-aware verification strategy, collaborate with architecture, RTL, formal, and performance teams, and drive reusable methodology and automation for scalable verification across cores, PMC, and uncore domains.