Principal Cache-Coherence Verification Architect

sifive; Santa Clara (CA); On-site; USD 180,000 - 290,000; Full time

Job summary

SiFive is seeking a Principal Design Verification Engineer to lead verification strategy for a scalable cache-coherent interconnect subsystem used in high-performance CPU and SoC platforms.

You will define architecture-aware verification approaches, work across architecture, RTL, formal, performance, and verification teams to verify data movement, protocol correctness, ordering, and QoS across multiple interfaces and bridges.

Qualifications

• BS/MS/PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 12+ years of CPU/subsystem/SoC/ASIC functional verification experience at Principal/T6 level.
• Strong hands-on SystemVerilog-based verification and reusable DV infrastructure.
• Deep understanding of cache-coherent systems, on-chip interconnects, memory-subsystem behavior, and related verification semantics.
• Experience creating verification plans, assertions, checkers, scoreboards, coverage models, and debug workflows.
• Strong debugging skills and ability to translate architectural intent into verification strategy.
• Proficiency in Python or similar languages for scalable DV infrastructure and workflows.
• Excellent technical communication across architecture, RTL, formal, performance, and verification teams.

Responsibilities

• Lead verification planning and execution for a cache-coherent interconnect subsystem from block level through subsystem integration and sign-off.
• Define verification strategy, test plans, closure criteria, assertions, checkers, scoreboards, stimulus approaches, and coverage models.
• Drive verification across interface boundaries, bridges, protocol adaptation layers, and data-movement paths.
• Develop high-value directed and constrained-random scenarios exposing corner cases in coherency and performance.
• Partner with architecture, RTL, and formal teams to review specs and improve verification quality before late-cycle issues.
• Drive root-cause analysis across spec, RTL, assertions, test content, and verification infrastructure for durable closure.
• Apply appropriate verification methods including simulation, formal techniques, emulation, and performance-oriented verification.
• Influence methodology and infrastructure across the broader interconnect verification effort.
• Mentor engineers and raise the technical bar through reviews and reusable infrastructure.

Skills

SystemVerilog

DV infrastructure

Cache-coherent systems

Interconnects

Debug & verification

Python scripting

Automation

Cross-functional communication

Education

BS/MS/PhD in Electrical Engineering/Computer Engineering/Computer Science

Tools

SystemVerilog

Verification frameworks

Job description

SiFive is seeking a Principal Design Verification Engineer to lead verification strategy for a scalable cache-coherent interconnect subsystem used in high-performance CPU and SoC platforms.

You will define architecture-aware verification approaches, work across architecture, RTL, formal, performance, and verification teams to verify data movement, protocol correctness, ordering, and QoS across multiple interfaces and bridges.