Principal ASIC Design Engineer — RTL & Silicon Bring-Up

SiMa.ai, Inc.; San Jose (CA); Hybrid; USD 204,000 - 316,000; Full time

Benefits offered by this job

Private company equity

Comprehensive benefits package

Job summary

SiMa.ai, Inc. in San Jose, CA seeks a Principal ASIC Design Engineer to own complex blocks from microarchitecture to silicon. You will lead RTL implementation, verification support, and silicon bring-up in a fast-paced startup setting.

The role collaborates with verification, physical design, architecture, and firmware teams to achieve timing, power, and area targets, with emphasis on high-quality, synthesizable RTL and DFT readiness.

Qualifications

• Master's degree required in Electrical/Computer Engineering or related field.
• 10+ years of ASIC design experience with block-level RTL and silicon bring-up.
• Proven track record taking blocks from microarchitecture to working silicon.

Responsibilities

• Own microarchitecture definition and RTL for complex blocks from concept to silicon.
• Drive ground-up block design from specification to RTL, integration, and bring-up.
• Develop high-quality, synthesizable RTL (Verilog/SystemVerilog) with data-path optimizations.
• Collaborate with verification, physical design, architecture, and firmware teams to meet targets.

Skills

RTL design

Verilog/SystemVerilog

Block-level ASIC design

DFT concepts

Synthesis & timing closure

Post-silicon validation

Education

Master's degree in Electrical Engineering or related field

Tools

Oscilloscopes

Logic analyzers

Protocol analyzers

Synthesis tools

Job description

SiMa.ai, Inc. in San Jose, CA seeks a Principal ASIC Design Engineer to own complex blocks from microarchitecture to silicon. You will lead RTL implementation, verification support, and silicon bring-up in a fast-paced startup setting.

The role collaborates with verification, physical design, architecture, and firmware teams to achieve timing, power, and area targets, with emphasis on high-quality, synthesizable RTL and DFT readiness.