Principal Analog/Mixed-Signal Architect-High-Speed SerDes

Astera Labs; Irvine (CA); On-site; USD 170,000 - 210,000; Full time

Benefits offered by this job

Discretionary bonus

Competitive equity

Job summary

Astera Labs is seeking a Principal Analog Design Engineer in Irvine, CA to architect and deliver high‑performance analog and mixed‑signal circuits powering SerDes, PHY, and high‑speed I/O. You will own designs from concept through silicon bring‑up, shaping the analog team's technical bar and mentoring engineers as we scale.

You will collaborate with digital, physical design, and systems teams to deliver end‑to‑end solutions, while optimizing for power, area, and performance.

Qualifications

• MS or PhD in Electrical Engineering or related field.
• 8+ years in analog and mixed-signal IC design.
• Proven track record with high-speed analog circuits (PLLs, SerDes, DACs/ADCs).
• Strong physical-layer design, SI, and high-speed I/O understanding.
• Experience with Cadence tools and layout-aware design.

Responsibilities

• Architect and design high-speed analog and mixed-signal circuits for SerDes, PLLs, references.
• Lead silicon bring-up, characterization, and debug across PVT.
• Mentor engineers and set design standards for the team.
• Define test plans to validate silicon performance against targets.

Skills

Analog design

Mixed-signal

SerDes

PLL design

High-speed IO

CMOS/FinFET

Power optimization

Education

MS/PhD EE

Tools

Cadence Virtuoso

Spectre

Job description

Astera Labs is seeking a Principal Analog Design Engineer in Irvine, CA to architect and deliver high‑performance analog and mixed‑signal circuits powering SerDes, PHY, and high‑speed I/O. You will own designs from concept through silicon bring‑up, shaping the analog team's technical bar and mentoring engineers as we scale.

You will collaborate with digital, physical design, and systems teams to deliver end‑to‑end solutions, while optimizing for power, area, and performance.