Lead Analog & Mixed-Signal Design Architect

Astera Labs; Irvine, Northern (CA, KY); Hybrid; USD 170,000 - 210,000; Full time

Benefits offered by this job

Discretionary bonus

Benefits

Job summary

Astera Labs in Irvine, CA is seeking a Principal Analog Mixed-Signal Design Engineer to architect and implement high-speed analog and mixed-signal circuits that anchor SerDes, PHY, and high-speed I/O — the silicon building blocks that move data for AI data centers.

You will own designs from concept through silicon bring-up, set the technical bar for the analog team, and mentor engineers as we scale. If you want your circuits to enable the next generation of AI compute, this is where that happens.

Qualifications

• 8+ years of analog/mixed-signal IC design experience.
• Experience with high-speed analog blocks (PLLs, SerDes, data converters).
• Strong understanding of physical-layer design and high-speed I/O.
• Proficiency with CMOS/FinFET processes and layout-aware design.

Responsibilities

• Architect and design high-speed analog/mixed-signal circuits (PLLs, LDOs, references, ADCs/DACs).
• Lead design from concept to silicon bring-up and verification across PVT corners.
• Define test plans and drive production tape-out readiness.
• Mentor junior engineers and set design standards across the team.
• Collaborate with digital, physical design, and systems teams to deliver full-chip solutions.

Skills

High-speed analog design

PLL/SerDes design

CMOS/FinFET knowledge

Signal integrity

Mentoring

Education

MS or PhD in Electrical Engineering

Tools

Cadence Virtuoso

Spectre

Job description

Astera Labs in Irvine, CA is seeking a Principal Analog Mixed-Signal Design Engineer to architect and implement high-speed analog and mixed-signal circuits that anchor SerDes, PHY, and high-speed I/O — the silicon building blocks that move data for AI data centers.

You will own designs from concept through silicon bring-up, set the technical bar for the analog team, and mentor engineers as we scale. If you want your circuits to enable the next generation of AI compute, this is where that happens.