Design Verification Lead – SerDes/PHY IP

Asteralabs; San Jose (CA); On-site; USD 160,000 - 200,000; Full time

Job summary

Astera Labs is seeking a Principal Design Verification Engineer to own the functional verification of high-speed SerDes/PHY IP. You will architect verification environments, drive coverage, and ensure first-pass silicon success on the analog/digital boundary for next-generation AI systems.

You will collaborate with PHY analog/mixed-signal designers, digital architects, and SoC teams to verify multi-Gbps SerDes blocks that power leading AI platforms, including UALink, UCIe, PCIe Gen 6/7, and

Qualifications

• Bachelor's degree in Electrical or Computer Engineering.
• 5+ years of design verification on high-speed SerDes/PHY/mixed-signal IP.
• Expert-level SystemVerilog and UVM proficiency.
• Experience with RNM and analog/mixed-signal co-simulation.
• Knowledge of PCIe, UALink, UCIe, Ethernet, or CXL SerDes/IP.

Responsibilities

• Architect UVM-based verification environments for SerDes/PHY IP, including PMA, PCS, and PHY-MAC interface layers.
• Define verification plans, coverage models, and sign‑off criteria for high-speed serial link blocks.
• Drive methodology decisions across analog/mixed-signal co-simulation, gate-level simulation, and emulation flows.
• Develop SystemVerilog/UVM testbenches, sequences, scoreboards, and reference models for multi-Gbps SerDes lanes.
• Lead coverage analysis and closure, debug failures with designers, and drive regressions to tape-out.
• Verify PHY behavior against PCIe Gen 6/Gen 7, UALink, UCIe, and Ethernet PHY standards.

Skills

Design verification

Physical layer knowledge

SystemVerilog & UVM

RNM & analog/mixed-signal

High-speed protocols (PCIe, UALink, Ue

Education

B.S. in Electrical/Computer Engineering

MS/PhD preferred

Tools

Palladium

Veloce

ZeBu

Job description

Astera Labs is seeking a Principal Design Verification Engineer to own the functional verification of high-speed SerDes/PHY IP. You will architect verification environments, drive coverage, and ensure first-pass silicon success on the analog/digital boundary for next-generation AI systems.

You will collaborate with PHY analog/mixed-signal designers, digital architects, and SoC teams to verify multi-Gbps SerDes blocks that power leading AI platforms, including UALink, UCIe, PCIe Gen 6/7, and