Lead Analog & Mixed-Signal Design Engineer, AI Connectivity

Asteralabs; Irvine (CA); On-site; USD 170,000 - 210,000; Full time

Benefits offered by this job

Discretionary bonus

Job summary

Astera Labs is seeking a Principal Analog Design Engineer to architect and deliver high-performance analog and mixed-signal circuits for SerDes, PHY, and high-speed I/O. You will own designs from concept to silicon bring-up, setting technical standards and mentoring the team to meet ambitious AI connectivity goals.

The role emphasizes deep expertise in CMOS/FinFET analog design, rigorous verification, and cross-functional collaboration with digital, physical design, and architecture teams to

Qualifications

• MS or PhD in Electrical Engineering or a related field.
• 8+ years of experience in analog and mixed-signal integrated circuit design.
• Proven track record designing high-speed analog circuits such as PLLs, SerDes front-ends, data converters, references, or regulators in advanced CMOS/FinFET nodes.
• Strong understanding of physical-layer design principles, signal integrity, and high-speed I/O.
• Proficiency with industry-standard design and simulation tools (e.g., Cadence Virtuoso, Spectre) and solid layout/parasitic-aware design skills.

Responsibilities

• Architect and design high-speed analog and mixed-signal circuits including PLLs, LDOs, references, high-speed SerDes building blocks, ADCs/DACs, and clocking.
• Drive circuit design from specification and architecture through schematic, layout supervision, and verification across PVT corners.
• Lead silicon bring-up, characterization, and debug, partnering with validation and product engineering to root-cause and resolve issues.

Skills

Analog Design

Mixed-Signal

PLLs

SerDes

Data Converters

Clocking

Circuit Verification

Mentoring

CMOS/FinFET

Education

MS in Electrical Engineering

PhD in Electrical Engineering

Tools

Cadence Virtuoso

Spectre

Job description

Astera Labs is seeking a Principal Analog Design Engineer to architect and deliver high-performance analog and mixed-signal circuits for SerDes, PHY, and high-speed I/O. You will own designs from concept to silicon bring-up, setting technical standards and mentoring the team to meet ambitious AI connectivity goals.

The role emphasizes deep expertise in CMOS/FinFET analog design, rigorous verification, and cross-functional collaboration with digital, physical design, and architecture teams to