Principal Analog Design Architect - High-Speed SerDes & I/O

Asteralabs; San Jose (CA); On-site; USD 207,000 - 230,000; Full time

Job summary

Astera Labs is redefining the connectivity that powers rack-scale AI infrastructure. As a Principal Analog Design Engineer, you will architect and design high-speed analog and mixed-signal circuits that anchor our SerDes, PHY, and high-speed I/O—silicon building blocks moving data at AI speeds.

This hands-on, high-impact role expects end-to-end ownership from concept to silicon bring-up, setting engineering standards, and mentoring teammates as we scale.

Qualifications

• MS or PhD in Electrical Engineering or a related field.
• 8+ years of experience in analog and mixed-signal integrated circuit design.
• Proven track record designing high-speed analog circuits such as PLLs, SerDes front-ends, data converters, references, or regulators in advanced CMOS/FinFET nodes.
• Strong understanding of physical-layer design principles, signal integrity, and high-speed I/O.
• Proficiency with industry-standard design and simulation tools (e.g., Cadence Virtuoso, Spectre) and solid layout/parasitic-aware design skills.

Responsibilities

• Architect and design high-speed analog and mixed-signal circuits including PLLs, LDOs, references, high-speed SerDes building blocks, ADCs/DACs, and clocking.
• Lead silicon bring-up, characterization, and debug, partnering with validation and product engineering to root-cause and resolve issues.
• Set analog design methodology, review standards, and best practices across the team.
• Partner cross-functionally with digital, physical design, systems, and architecture teams to deliver full-chip solutions.

Skills

Analog & Mixed-Signal Design

High-speed I/O

Cadence Virtuoso

Spectre

CMOS/FinFET process nodes

Education

MS or PhD in Electrical Engineering

Tools

Cadence Virtuoso

Spectre

Job description

Astera Labs is redefining the connectivity that powers rack-scale AI infrastructure. As a Principal Analog Design Engineer, you will architect and design high-speed analog and mixed-signal circuits that anchor our SerDes, PHY, and high-speed I/O—silicon building blocks moving data at AI speeds.

This hands-on, high-impact role expects end-to-end ownership from concept to silicon bring-up, setting engineering standards, and mentoring teammates as we scale.