Principal DRAM Memory Design Engineer - Lead Innovation

Micron Technology, Inc; Boise (ID); Sur place; USD 180 000 - 260 000; Plein temps

Avantages offerts par ce poste

Relocation assistance

Medical, dental, vision plans

Paid time off

Holiday pay

Résumé du poste

Micron Technology, Inc in Boise, ID seeks a Principal SMTS/ MTS DRAM Memory Design Engineer to lead digital and analog circuit design for next-generation memory products. You will drive verification, silicon validation, and parasitic analysis while guiding optimization efforts.

The role requires strong leadership, cross-functional collaboration, and expertise in Verilog, PDN analysis, and AI-assisted design flows. On-site 5 days with relocation support possible.

Qualifications

• Bachelor's in Electrical Engineering with 10+ years for BSEE track or 15+ years for SMTS track.
• Strong CMOS circuit design knowledge and Verilog modeling experience.
• Experience with design verification methodologies and power delivery networks.

Responsabilités

• Design and optimize digital and analog circuits for next-generation DRAM products.
• Lead circuit development, simulation, verification, and silicon validation.
• Drive floor-planning, layout optimization, and tape-out activities.
• Mentor engineers and collaborate across internal/external partners.

Connaissances

CMOS circuit design

Verilog

Design verification

Scripting (Python/Tcl/Perl)

Analytical thinking

Cross-functional collaboration

Formation

Bachelor's degree in Electrical Engineering

MSEE or related master's preferred

15+ years semiconductor design experience (SMTS path)

Outils

HSPICE

FINESIM

PDN analysis tools

Description du poste

Micron Technology, Inc in Boise, ID seeks a Principal SMTS/ MTS DRAM Memory Design Engineer to lead digital and analog circuit design for next-generation memory products. You will drive verification, silicon validation, and parasitic analysis while guiding optimization efforts.

The role requires strong leadership, cross-functional collaboration, and expertise in Verilog, PDN analysis, and AI-assisted design flows. On-site 5 days with relocation support possible.