Physical Design Engineer: Shape Next-Gen SoCs & IP

Intel; Boxborough (MA); On-site; USD 91,000 - 149,000; Full time

Benefits offered by this job

Health benefits

Stock bonuses

Retirement plan

Vacation

Job summary

Intel is seeking a College Grad Physical Design Engineer to help drive the next generation of semiconductor innovations in Massachusetts. You will participate in physical design for custom IP and SoC implementations, guiding RTL through GDS with a focus on power, performance, and area.

You will apply expertise in synthesis, place-and-route, STA, and verification, collaborating across teams to deliver robust, manufacturable designs that meet timing and reliability requirements.

Qualifications

• Bachelor's or Master's in Electrical/Computer Engineering or related field with 0–1 years of physical design experience per business needs.
• RTL design experience and timing closure knowledge to optimize semiconductor performance.
• Experience with TCL scripting.
• Strong problem-solving and analytical abilities.

Responsibilities

• Perform physical design implementation of custom IP and SoC designs from RTL to GDS.
• Execute synthesis, place and route, clock tree synthesis, floor planning, and STA.
• Conduct power and noise analysis and power/clock distribution optimization.
• Verify designs using EDA verification methods and reliability checks.
• Identify and resolve design violations and improve product architectures.
• Optimize designs for power, performance, and area using industry-standard tools.
• Help develop and refine physical design methodologies and flows.

Skills

Physical design tools

RTL design experience

Timing closure knowledge

TCL scripting

Education

Bachelor's degree in E.E./C.E.

Tools

Logic synthesis tools

Place & route tools

Static timing analysis tools

Layout verification tools

Job description

Intel is seeking a College Grad Physical Design Engineer to help drive the next generation of semiconductor innovations in Massachusetts. You will participate in physical design for custom IP and SoC implementations, guiding RTL through GDS with a focus on power, performance, and area.

You will apply expertise in synthesis, place-and-route, STA, and verification, collaborating across teams to deliver robust, manufacturable designs that meet timing and reliability requirements.