Impactful CPU Core Physical Design Engineer (RTL-to-GDS)

Intel Corporation; Hillsboro (OR); On-site; USD 122,000 - 232,000; Full time

Job summary

Intel Corporation in Hillsboro, Oregon is seeking a Mid-level Physical Design Engineer for CPU cores. You will execute RTL-to-GDS flows, including synthesis, floorplanning, PnR, STA, and power analysis to meet timing and power targets.

Join a team that collaborates across RTL, verification, clocking, and full-chip teams, develops design flows, and mentors growth through hands-on silicon design at advanced nodes.

Qualifications

• Bachelor's in Computer/Electrical Engineering or related field with 5+ years of relevant work experience.
• Or a Masters in the same field with 3+ years of relevant work experience.
• Experience with integrated circuit design tools (e.g., Synopsys/Cadence), including logic synthesis, place and route, STA and design closure.
• PV convergence including static timing and power analysis.
• Chip physical design verification including DRC/LVS, noise and electromigration checks.
• Scripting in an interpreted language, TCL plus at least one more (e.g., Perl, Python, Ruby).

Responsibilities

• Execute physical design implementation for CPU core blocks or subsystems.
• Perform synthesis, floorplanning, place and route, and design closure activities.
• Conduct static timing analysis, power analysis, and physical verification.
• Identify and debug timing, power, and design rule violations.
• Contribute to achieving timing, power, and area targets.
• Develop and maintain scripts for design automation (TCL, Python).
• Collaborate with RTL design, verification, clocking, and full-chip teams.

Skills

TCL scripting

Python scripting

Problem solving

Cross-functional teamwork

Education

Bachelor's degree in EE/CS

Master's degree in EE/CS

Tools

Synopsys/Cadence tools

ICC2 / PrimeTime

Genus / Innovus

Job description

Intel Corporation in Hillsboro, Oregon is seeking a Mid-level Physical Design Engineer for CPU cores. You will execute RTL-to-GDS flows, including synthesis, floorplanning, PnR, STA, and power analysis to meet timing and power targets.

Join a team that collaborates across RTL, verification, clocking, and full-chip teams, develops design flows, and mentors growth through hands-on silicon design at advanced nodes.