CPU Core Physical Design Engineer — Growth & Impact

Intel; Hillsboro (OR); On-site; USD 122,000 - 232,000; Full time

Benefits offered by this job

Stock bonuses

Intel Benefits

Health benefits

Retirement plan

Vacation

Job summary

Intel in Hillsboro, Oregon seeks a Mid-level Physical Design Engineer to contribute to high-performance silicon across client, server, IoT, and AI platforms. You will own RTL-to-GDS tasks for CPU core blocks and collaborate with cross-functional teams to meet aggressive PPA targets.

Responsibilities include synthesis, floorplanning, PnR, STA, and design closure, with scripting in TCL and Python to automate flows. The role offers growth in physical design and SoC development within a dynamic team.

Qualifications

• Experience with integrated circuit design tools including logic synthesis, place and route, STA and design closure.
• PV convergence including static timing and power analysis.
• Chip physical design verification including DRC/LVS and noise checks.
• Scripting languages TCL and at least one other (Python/Perl).
• Experience synthesizing digital blocks into large SoCs or IP.

Responsibilities

• Execute physical design implementation for CPU core blocks or subsystems.
• Perform synthesis, floor planning, PnR, and design closure activities.
• Conduct static timing analysis, power analysis, and physical verification.
• Identify and debug timing, power, and design rule violations.
• Develop scripts for design automation (TCL, Python).
• Collaborate with RTL design, verification, clocking, and full-chip teams.

Skills

IC design tools

Synthesis & PnR

STA & Power analysis

Design closure

RTL-to-GDS

Scripting TCL/Python

Cross-functional collaboration

Education

Bachelor's in Electrical/Computer Engineering

Master's in Electrical/Computer Engineering

Tools

Synopsys tools

Cadence tools

PrimeTime

Genus/Innovus

Job description

Intel in Hillsboro, Oregon seeks a Mid-level Physical Design Engineer to contribute to high-performance silicon across client, server, IoT, and AI platforms. You will own RTL-to-GDS tasks for CPU core blocks and collaborate with cross-functional teams to meet aggressive PPA targets.

Responsibilities include synthesis, floorplanning, PnR, STA, and design closure, with scripting in TCL and Python to automate flows. The role offers growth in physical design and SoC development within a dynamic team.