Physical Design Engineer: RTL to GDS for High-Speed IP

VIVA USA Inc; Santa Clara (CA); On-site; USD 150,000 - 190,000; Full time

Job summary

VIVA USA Inc. is seeking a Senior Silicon Design Engineer to drive RTL to GDS flows for high-speed datapath IP on site in Santa Clara, CA. You will lead automated synthesis, timing-driven place and route, CTS, clock gating, and power/area optimizations for advanced nodes.

Responsibilities include floor planning, design methodology, logic equivalence checks, and final IP signoff. Strong Verilog and multi-project coordination are essential for success.

Qualifications

• Major in EE, CS or related, master’s degree with 3+ years or Bachelor with 5+ years working experience, preferably with high designs or other high-performance IP designs.
• Experience in automated synthesis and timing driven place and route of RTL blocks (Verilog experience preferred) for high speed Datapath and control logic applications. Mainly in ICC2, fusion compiler, calibre and Prime Time.
• Experience in automated design flows for clock tree synthesis, clock gating techniques, buffer/repeater insertion, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction
• Strong background in digital circuit techniques, efficient and robust implementation topologies for logic functions, logic optimization, and transistor level circuit topologies for high speed, low power applications

Responsibilities

• This engineer will work on leading edge technology nodes designs.
• This includes automated synthesis and timing driven place and route of RTL blocks for high speed Datapath and control logic applications, automated design flows for clock tree synthesis, clock gating techniques, buffer/repeater insertion, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction.
• You will also support floor planning, establishing design methodology, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery.

Skills

RTL to GDS

Place & Route

Synthesis

Timing analysis

Verilog

Clock tree synthesis

Power optimization

Education

Master's degree in EE/CS

Bachelor's degree in EE/CS

Tools

ICC2

Fusion Compiler

Calibre

PrimeTime

Job description

VIVA USA Inc. is seeking a Senior Silicon Design Engineer to drive RTL to GDS flows for high-speed datapath IP on site in Santa Clara, CA. You will lead automated synthesis, timing-driven place and route, CTS, clock gating, and power/area optimizations for advanced nodes.

Responsibilities include floor planning, design methodology, logic equivalence checks, and final IP signoff. Strong Verilog and multi-project coordination are essential for success.