Physical Design Engineer

Infotree Global Solutions; Santa Clara (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

Infotree Global Solutions seeks an engineer to work on leading-edge technology node designs, including automated synthesis and timing-driven place-and-route for RTL datapath and control logic.

The role involves floor planning, establishing design methodology, and checks for logic equivalence and signoff for large IP delivery, with focus on reducing design cycle time and improving timing/power/area.

Qualifications

• Master’s degree in EE/CS with 3+ years or Bachelor with 5+ years in high-design IP.
• Experience with automated synthesis and timing-driven P&R of RTL blocks (Verilog preferred).
• Proficiency with ICC2, Fusion Compiler, Calibre and PrimeTime.

Responsibilities

• Lead automated synthesis and timing-driven P&R for RTL datapath and control logic.
• Support floor planning, methodology, and checks for logic equivalence and physical/timing/electrical quality.
• Perform final signoff for large IP delivery and reduce design cycle time.

Skills

RTL design

Timing-driven P&R

Verilog experience

Education

Master’s in EE/CS

Bachelor in EE/CS

Tools

ICC2

Fusion Compiler

Calibre

PrimeTime

Job description

This engineer will work on leading edge technology nodes designs. This includes automated synthesis and timing driven place and route of RTL blocks for high speed Datapath and control logic applications, automated design flows for clock tree synthesis, clock gating techniques, buffer/repeater insertion, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. You will also support floor planning, establishing design methodology, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery.

SKILL SETS:

• Major in EE, CS or related, master’s degree with 3+ years or Bachelor with 5+ years working experience, preferably with high designs or other high-performance IP designs.
• Experience in automated synthesis and timing driven place and route of RTL blocks (Verilog experience preferred) for high speed Datapath and control logic applications.
• Mainly in ICC2, fusion compiler, calibre and Prime Time.