Hardware Physical Design Engineer

VIVA USA Inc; Santa Clara (CA); Sur place; USD 150 000 - 190 000; Plein temps

Résumé du poste

VIVA USA Inc. is seeking a Senior Silicon Design Engineer to drive RTL to GDS flows for high-speed datapath IP on site in Santa Clara, CA. You will lead automated synthesis, timing-driven place and route, CTS, clock gating, and power/area optimizations for advanced nodes.

Responsibilities include floor planning, design methodology, logic equivalence checks, and final IP signoff. Strong Verilog and multi-project coordination are essential for success.

Qualifications

• Major in EE, CS or related, master’s degree with 3+ years or Bachelor with 5+ years working experience, preferably with high designs or other high-performance IP designs.
• Experience in automated synthesis and timing driven place and route of RTL blocks (Verilog experience preferred) for high speed Datapath and control logic applications. Mainly in ICC2, fusion compiler, calibre and Prime Time.
• Experience in automated design flows for clock tree synthesis, clock gating techniques, buffer/repeater insertion, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction
• Strong background in digital circuit techniques, efficient and robust implementation topologies for logic functions, logic optimization, and transistor level circuit topologies for high speed, low power applications

Responsabilités

• This engineer will work on leading edge technology nodes designs.
• This includes automated synthesis and timing driven place and route of RTL blocks for high speed Datapath and control logic applications, automated design flows for clock tree synthesis, clock gating techniques, buffer/repeater insertion, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction.
• You will also support floor planning, establishing design methodology, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery.

Connaissances

RTL to GDS

Place & Route

Synthesis

Timing analysis

Verilog

Clock tree synthesis

Power optimization

Formation

Master's degree in EE/CS

Bachelor's degree in EE/CS

Outils

ICC2

Fusion Compiler

Calibre

PrimeTime

Description du poste

Senior Silicon Design Engineer

THE ROLE:

This is a Physical Design Engineering role that will require to take the design from RTL to GDS with synthesis, Place n Route, timing, and Physical Verification

THE PERSON:

Strong communication skills, ability to multi-task across projects, and work with geographically spread-out teams

RESPONSIBILTIES:

• This engineer will work on leading edge technology nodes designs.
• This includes automated synthesis and timing driven place and route of RTL blocks for high speed Datapath and control logic applications, automated design flows for clock tree synthesis, clock gating techniques, buffer/repeater insertion, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction.
• You will also support floor planning, establishing design methodology, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery.

PREFERRED SKILLED SETS:

• Major in EE, CS or related, master’s degree with 3+ years or Bachelor with 5+ years working experience, preferably with high designs or other high-performance IP designs.
• Experience in automated synthesis and timing driven place and route of RTL blocks (Verilog experience preferred) for high speed Datapath and control logic applications. Mainly in ICC2, fusion compiler, calibre and Prime Time.
• Experience in automated design flows for clock tree synthesis, clock gating techniques, buffer/repeater insertion, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction
• Strong background in digital circuit techniques, efficient and robust implementation topologies for logic functions, logic optimization, and transistor level circuit topologies for high speed, low power applications

EDUCATION:

• Major in EE, CS or related, master’s degree preferably with high-speed multi-gigabit SerDes PHY designs or other high-performance IP designs.

Notes:

• Onsite 5 days a week

VIVA is an equal opportunity employer. All qualified applicants have an equal opportunity for placement, and all employees have an equal opportunity to develop on the job. This means that VIVA will not discriminate against any employee or qualified applicant on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability or protected veteran status