Hardware Physical Design Engineer - RTL-to-GDS & PPA Expert

Infotree Global Solutions; Santa Clara (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

Infotree Global Solutions is looking for a Senior IC Physical Design engineer to drive RTL-to-GDS synthesis, place and route, and timing analysis for high-speed datapath designs.

You will perform floorplanning, clock tree synthesis, scan stitching, and optimize for power, performance, and area (PPA), ensuring timing and physical signoff. This role requires deep experience with industry tools and flows.

Qualifications

• Experience in RTL/Verilog design and verification.
• Strong background in physical design flows including synthesis and P&R.
• Familiar with timing analysis and signoff for high-speed datapath.
• Knowledge of industry tools ICC2, Fusion Compiler, Calibre, PrimeTime.

Responsibilities

• Translate RTL designs to GDSII through synthesis, place and route.
• Perform floorplanning and clock tree synthesis for performance.
• Conduct timing analysis and physical verification to ensure signoff.
• Optimize designs for power, performance, and area (PPA).

Skills

RTL/Verilog

Physical Design

Synthesis

Place and Route

Timing Analysis

ICC2

Fusion Compiler

Calibre

PrimeTime

Clock Tree Synthesis

PPA Optimization

Tools

ICC2

Fusion Compiler

Calibre

PrimeTime

Clock Tree Synthesis (CTS)

Job description

Infotree Global Solutions is looking for a Senior IC Physical Design engineer to drive RTL-to-GDS synthesis, place and route, and timing analysis for high-speed datapath designs.

You will perform floorplanning, clock tree synthesis, scan stitching, and optimize for power, performance, and area (PPA), ensuring timing and physical signoff. This role requires deep experience with industry tools and flows.