Physical Design Engineer

Infobahn Softworld Inc; Santa Clara (CA); On-site; USD 120,000 - 190,000; Full time

Job summary

Infobahn Softworld Inc in Santa Clara, CA, is seeking a Physical Design Engineer to take RTL to GDS with synthesis, place-and-route, timing, and physical verification, driving high-speed Datapath and control logic blocks.

You will collaborate with geographically distributed teams, automate design flows for clock tree synthesis, power gating, buffer insertion, and sign-off for large IP, ensuring timing, power and area targets are met.

Qualifications

• 2-5+ years in high-speed SerDes PHY or high-performance IP designs.
• Proficiency in Python and/or Perl; other languages are a plus.
• Experience with automated design flows for RTL, synthesis, and P&R.
• RTL to GDS flow with timing-driven P&R for datapath and control logic.
• Experience in floor planning, IP integration, and sign-off processes.
• Familiarity with schematics, layout, and circuit simulation tools.

Responsibilities

• Lead RTL-to-GDS flow including synthesis, P&R, timing, and physical verification.
• Perform floor planning and IP integration; ensure design checks for quality.
• Develop automated design flows for clock tree synthesis, gating, and optimization.
• Collaborate with distributed teams to meet cycle-time targets.
• Support final sign-off for large IP delivery.

Skills

RTL to GDS

Place & Route

Synthesis

Timing Analysis

Python

Perl

Verilog

Clock Tree Synthesis

Floor Planning

Education

Master’s degree in EE/CS

Tools

Schematics

Layout

Circuit/Logic Simulation

Job description

This is a Physical Design Engineering role that will require to take the design from RTL to GDS with synthesis, Place n Route, timing, and Physical Verification

THE PERSON:

Strong communication skills, ability to multi-task across projects, and work with geographically spread-out teams

RESPONSIBILTIES:

This engineer will work on high-speed multi-gigabit SerDes PHY designs. This includes automated synthesis and timing driven place and route of RTL blocks for high speed Datapath and control logic applications, automated design flows for clock tree synthesis, clock and power gating techniques, buffer/repeater insertion, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. You will also support floor planning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery.

PREFERRED SKILLED SETS:

• 2-5+ years working experience, preferably with high-speed multi-gigabit SerDes PHY designs or other high-performance IP designs
• Proficiency in Python and/or Perl is required. Additional languages are a plus.
• Versatility with scripts to automate design flow, and quality checks.
• Experience in automated synthesis and timing driven place and route of RTL blocks (Verilog experience preferred) for high speed Datapath and control logic applications.
• Experience in automated design flows for clock tree synthesis, clock and power gating techniques, buffer/repeater insertion, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction
• Strong background in digital circuit techniques, efficient and robust implementation topologies for logic functions, logic optimization, and transistor level circuit topologies for high speed, low power applications
• Experience in floor planning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery.
• Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation

EDUCATION:

Major in EE, CS or related, master’s degree preferably with high-speed multi-gigabit SerDes PHY designs or other high-performance IP designs.