PD Methodology Engineer II: Cloud-Scale ASIC Flows

Amazon; Cupertino, Northern (CA, KY); Hybrid; USD 157,000 - 213,000; Full time

Benefits offered by this job

Health insurance

RSUs & sign-on

401(k) matching

Job summary

Amazon is seeking a hardware design professional to lead the development of physical design methodologies and CAD flows for high-performance data-center ASICs. You will contribute to the AWS Inferentia ecosystem, shaping PPA-aware design flows and toolchains while collaborating with RTL, PD, and DFT teams to optimize cost, quality, and performance.

The role requires hands-on scripting in TCL/Perl/Python, strong ASIC design knowledge, and experience with PD tools like Innovus, ICC2, and

Qualifications

• Bachelor's degree in Electrical Engineering or a related field.
• Minimum of 3+ years in developing design methodology or CAD flows in synthesis, PNR, or sign-off areas for advanced technology nodes.
• Experience in writing production scripts for implementation and sign-off tools in TCL, Perl, and/or Python.
• Solid understanding of ASIC physical design, physical design flows, and methodologies including synthesis, place and route, STA, formal verification
• Proven track record of delivering metric driven PPA flow development and support

Responsibilities

• Create and support innovative physical design methodology and CAD flows.
• Develop cloud infrastructure to support physical design work.
• Drive improvement in RTL2GDS flows/methodology for PPA and TAT improvement.
• Create Dashboard/central reports for project tracking and visualizing QoR/stats.
• Interface directly with RTL, Physical Design, Package Design, DFT and other teams to improve methodologies and efficiencies and drive efforts to resolution.
• Work with EDA tool vendors to evaluate new tools, solve bugs, improve usability, etc.

Skills

Python

C/C++

TCL

Perl

Verilog/VHDL

Education

Bachelor's degree in Electrical Engineering or related field

Tools

Innovus

ICC2

FusionCompiler

STA

Job description

Amazon is seeking a hardware design professional to lead the development of physical design methodologies and CAD flows for high-performance data-center ASICs. You will contribute to the AWS Inferentia ecosystem, shaping PPA-aware design flows and toolchains while collaborating with RTL, PD, and DFT teams to optimize cost, quality, and performance.

The role requires hands-on scripting in TCL/Perl/Python, strong ASIC design knowledge, and experience with PD tools like Innovus, ICC2, and