Emulation Verification Engineer – SoC on Palladium

Apple Inc.; Sunnyvale (CA); On-site; USD 184,700 - 324,800; Full time

Job summary

Apple Inc. is seeking an experienced Emulation Verification engineer to verify large SoCs by porting designs to Palladium and building end-to-end test plans.

You will collaborate with Architecture, Design, DV, Silicon Validation, Power and SW teams to enable scalable emulation-based verification and develop SV/Verilog code and UVM test environments. The role emphasizes low-power testing, synthesizable monitors, and robust stimulus generation, with opportunities to advance in a fast-moving

Qualifications

• Minimum of BS with significant industry experience (10+ years).
• Strong understanding of SV/Verilog, UVM, and emulation workflows.
• Experience with FPGA/Emulation toolchains (Palladium/Veloce/Zebu).
• Proficient in SystemVerilog verification environments including DPI, UVM.

Responsibilities

• Port the design onto the Palladium emulation platform and complete test plans.
• Collaborate with Architecture, Design, DV, Silicon Validation, Power and SW teams.
• Develop/apply synthesizable monitors, checkers, and stimulus on emulation platform.
• Prepare and review test plans with multi-functional teams.
• Perform low power testing on the emulation platform.
• Develop code for design/verification using Verilog/SystemVerilog/UVM.
• Develop random stimulus infrastructure using UVM constraints.

Skills

SystemVerilog / Verilog

UVM

C/C++ DPI

Scripting: Perl/Python/TCL

Emulation verification

Debug skills

Education

BS degree in Electronics/related field

Tools

Palladium

Veloce

Zebu

Xilinx/Altera FPGA flow

Job description

Apple Inc. is seeking an experienced Emulation Verification engineer to verify large SoCs by porting designs to Palladium and building end-to-end test plans.

You will collaborate with Architecture, Design, DV, Silicon Validation, Power and SW teams to enable scalable emulation-based verification and develop SV/Verilog code and UVM test environments. The role emphasizes low-power testing, synthesizable monitors, and robust stimulus generation, with opportunities to advance in a fast-moving