Emulation Verification Engineer: SoC Bring-up on Palladium

Apple Inc.; Beaverton (OR); On-site; USD 120,000 - 150,000; Full time

Job summary

Apple Inc. seeks an Emulation Verification engineer to port designs onto the Palladium platform and complete detailed emulation test plans. You will collaborate with Architecture, Design, DV, Silicon Validation, Power and SW teams to bring up large SoCs on emulation platforms.

Key duties include developing synthesizable monitors, preparing test plans, performing low power tests, and writing verification code in Verilog/SystemVerilog/UVM, with stimulus infrastructure built on UVM constraints.

Qualifications

• BS degree with 3+ years of relevant industry experience.
• Experience writing synthesizable SystemVerilog/Verilog code and SystemVerilog assertions.
• Experience with SystemVerilog verification environments including C/C++ DPI, UVM.
• Understanding of the tool flow from RTL to Emulation is a plus.

Responsibilities

• Collaborate closely with Architecture, Design, DV, Silicon Validation, Power and SW teams to bring up large SoCs on emulation platform
• Develop/apply synthesizable monitors/checkers, stimulus on emulation platform
• Prepare and complete the test plan and perform reviews with the multi-functional teams
• Perform low power testing on emulation platform
• Develop code for Design and verification that aids with emulation activities, using Verilog/System Verilog/UVM
• Develop random stimulus infrastructure by reusing existing UVM simulation constraints

Skills

Verilog/SystemVerilog

UVM

C/C++ DPI

Test planning

Emulation verification

Education

Bachelor's degree

Tools

Palladium

Veloce

Zebu

Xilinx FPGA

Altera FPGA

Job description

Apple Inc. seeks an Emulation Verification engineer to port designs onto the Palladium platform and complete detailed emulation test plans. You will collaborate with Architecture, Design, DV, Silicon Validation, Power and SW teams to bring up large SoCs on emulation platforms.

Key duties include developing synthesizable monitors, preparing test plans, performing low power tests, and writing verification code in Verilog/SystemVerilog/UVM, with stimulus infrastructure built on UVM constraints.