Memory Packaging Architect: High-Bandwidth Systems

Apple, Inc.; United States; On-site; USD 185,000 - 325,000; Full time

Benefits offered by this job

Stock options

Employee stock purchase plan

RSU eligibility

Medical and dental coverage

Retirement plan

Relocation assistance

Job summary

Apple, Inc. in the San Francisco Bay Area is seeking a Memory Packaging Engineer to architect memory solutions powering next-gen Apple hardware. You will drive the memory package lifecycle from concept to qualification, collaborating with internal teams and external vendors.

You will define architectures, coordinate with mechanical, electrical, and thermal teams, and push for high-bandwidth, low-power designs. Excellent communication and deep packaging expertise are essential.

Qualifications

• BS and 10+ years of relevant industry experience.
• MS or PhD preferred, with 10+ years in package design and assembly.
• Expertise in thin-die stacking technologies such as wirebond, flip-chip, and wafer/die bonding.
• Strong knowledge of packaging materials and design to manage warpage and CTE.
• Experience in package test, reliability, and system-level interactions.
• Deep understanding of SI/PI co-design with memory die and high-speed signaling.

Responsibilities

• Define next-generation memory package architecture by evaluating technologies.
• Collaborate cross-functionally to solve electrical, mechanical, and thermal challenges.
• Drive vendor DOEs and failure analysis to improve yield and reliability.
• Define the memory package plan of record: form factor, process, layout, BOM.
• Guide memory vendors to develop materials and technologies for advanced designs.

Skills

10+ years experience

Strong communication

Thin-die stacking

Wirebond / Flip-chip

Wafer/die bonding

Packaging materials knowledge

Reliability / test understanding

Education

BS degree

MS or PhD preferred

Job description

Apple, Inc. in the San Francisco Bay Area is seeking a Memory Packaging Engineer to architect memory solutions powering next-gen Apple hardware. You will drive the memory package lifecycle from concept to qualification, collaborating with internal teams and external vendors.

You will define architectures, coordinate with mechanical, electrical, and thermal teams, and push for high-bandwidth, low-power designs. Excellent communication and deep packaging expertise are essential.