Memory Packaging Engineer

Apple; United States; On-site; USD 140,000 - 230,000; Full time

Job summary

Apple is seeking a Memory Packaging Engineer to architect memory solutions powering its high-performance hardware. You will drive the definition, development, and qualification of next-generation memory packages and guide roadmaps with memory partners, collaborating with internal teams to enable bandwidth and density scaling.

Your ownership spans the entire product lifecycle, from initial concept through qualification, with a focus on SI/PI co-design and mitigating thermal challenges in

Qualifications

• BS and 10+ years of relevant industry experience.
• MS or PhD preferred, with 10+ years of industry experience in package design and assembly process development.

Responsibilities

• Define memory packaging architecture and roadmaps.
• Collaborate with memory die design teams and internal engineering groups.
• Oversee qualification from concept to production for high-bandwidth memory packages.

Skills

Memory packaging

Interconnect design

System integration

Co-design

Vendor collaboration

Education

Bachelor's degree in Electrical Engineering or related field

Master's degree

PhD

Tools

Wirebond

Flip-chip

Wafer/die bonding

Job description

Join the team at the heart of memory innovation for every Apple product. As a Memory Packaging Engineer, you will architect the memory solutions that power the industry-leading performance of Apple's hardware. We push the boundaries of bandwidth density, power efficiency, and system integration through meticulous co-design between memory technology and our world-class systems. If you are driven to solve the industry's toughest packaging challenges, your work will have a profound and lasting impact on the products used by millions.

In this role, you will drive the definition, development, and qualification of next-generation memory packages critical to Apple’s future products.
You will guide the package roadmaps of our memory partners and collaborate with internal engineering teams to enable bandwidth and density scaling.
Your ownership will span the entire product lifecycle, from initial concept through qualification.

Minimum Qualifications

BS and 10+ years of relevant industry experience.

Preferred Qualifications

MS or PhD preferred, with 10+ years of industry experience in package design and assembly process development of high-bandwidth and high-density memory packages.
Strong knowledge of thin-die stacking technologies including wirebond, flip-chip, and wafer/die bonding.
Strong knowledge of packaging materials and design to engineer warpage and CTE properties and mitigate thermal challenges.
Solid working experience in package test and reliability, system-level downstream process interaction, and packaging inspection metrology.
Deep understanding of SI/PI co-design with memory die and high-speed DDR or differential signaling.
Understanding of how memory die floorplan and architecture influence package structure and routing, with experience collaborating with memory die design teams.
Excellent communication skills for collaborating with internal teams and managing external vendors.