Senior Manager, High-Speed Analog & LPDDR PHY Design

AMD; California (MO); Hybrid; USD 180,000 - 260,000; Full time

Benefits offered by this job

AMD benefits at a glance

Job summary

AMD seeks a senior engineer to lead the Memory I/O design team, focusing on LPDDR PHYs, circuit architecture and high-speed data-path calibration. You will collaborate across Analog/MIXED signal, Digital, Firmware and Verification to ensure robust designs and silicon success.

You will manage multiple IPs, develop link-level models, and guide RTL and FW implementations while defining development flows to boost efficiency and quality.

Qualifications

• Experience leading multiple PHY designs with silicon results.
• Circuit-architecture and modeling for High Speed IOs.
• Solid knowledge of equalization/calibration/clocking techniques.
• Knowledge of PHY modeling tools and Verilog/AMS.
• IO and system integration expertise.
• Ability to dive into RTL or FW code for custom designs.
• Minimum 5+ years of team management experience.

Responsibilities

• Define and design architecture for LPDDR PHYs and low-power blocks.
• Collaborate with Analog Mixed Signal, Digital Design, Firmware and Verification teams.
• Manage execution and deliverables across customers and stakeholders.
• Develop models for link-level performance simulations and training.
• Document micro-architecture and algorithms; guide cross-disciplinary teams.
• Contribute to development flows to improve efficiency and quality.

Skills

PHY design leadership

High Speed IO modeling

Algorithm calibration

RTL FW access

Signal integrity

Clocking techniques

Team management

Education

Bachelor's/Master/PhD in Computer/Electrical Engineering

Tools

Matlab/Simulink

Verilog/AMS

PHY modelling tools

Job description

AMD seeks a senior engineer to lead the Memory I/O design team, focusing on LPDDR PHYs, circuit architecture and high-speed data-path calibration. You will collaborate across Analog/MIXED signal, Digital, Firmware and Verification to ensure robust designs and silicon success.

You will manage multiple IPs, develop link-level models, and guide RTL and FW implementations while defining development flows to boost efficiency and quality.