Senior RTL Design Engineer — DDR/LPDDR Memory Controller

Advanced Micro Devices

Austin (TX)

On-site

USD 120,000 - 180,000

Full time

14 days+

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Benefits offered by this job

AMD benefits

Job summary

Advanced Micro Devices is seeking an RTL Design Engineer to join the Memory Controller Design team in Austin, TX. You will contribute to creating high‑quality IP features and RTL implementations for next‑gen memory controllers, working with architects and verification engineers across global teams.

You will analyze designs for power, performance, and area, perform lint and timing analyses, and participate in reviews.

Qualifications

  • Experience with digital logic design and RTL development.
  • Proficiency with Verilog or SystemVerilog.
  • Scripting in Python/Perl/Tcl.
  • Understanding of computer architecture and memory systems.
  • Experience with DDR/LPDDR memory is a plus.
  • Familiarity with EDA tools, lint, and synthesis workflows.
  • Background in digital logic verification is preferred.
  • Ability to work independently and with teams.

Responsibilities

  • Define and implement IP microarchitecture features with architects.
  • Develop RTL designs for IP features.
  • Analyze and optimize designs for power, performance and area.
  • Perform lint, CDC, and timing analysis and participate in design and code reviews.
  • Collaborate with verification engineers to validate IP throughout the project lifecycle.

Skills

Digital logic design
Verilog
SystemVerilog
Python
Perl
Tcl
Computer architecture
DDR memory systems
LPDDR memory systems
EDA tools
Digital logic verification
Independent collaboration
Written and verbal communication
Problem analysis

Education

Bachelor’s or Master’s in Computer Engineering / Electrical Engineering / Computer Science

Tools

EDA tools & design flows

Job description

Advanced Micro Devices is seeking an RTL Design Engineer to join the Memory Controller Design team in Austin, TX. You will contribute to creating high‑quality IP features and RTL implementations for next‑gen memory controllers, working with architects and verification engineers across global teams.

You will analyze designs for power, performance, and area, perform lint and timing analyses, and participate in reviews.

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