Senior RTL Design Engineer — DDR/LPDDR Memory IP

AMD; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

AMD is seeking an RTL Design Engineer to join the Memory Controller Design team in Austin, TX. You will contribute to IP microarchitecture features and RTL implementations, working closely with architects and verification engineers to deliver high-quality designs for advanced memory technologies.

You should have strong digital logic design experience, proficiency in Verilog/SystemVerilog, and comfort with Python/Perl/Tcl scripting for flows and automation.

Qualifications

• Bachelor’s or Master’s degree in computer engineering, electrical engineering, computer science, or a related technical field.
• Experience with digital logic design and computer architecture concepts.
• Strong written and verbal communication skills; ability to work across teams.

Responsibilities

• Define and implement IP microarchitecture features with architects.
• Develop RTL designs for IP features and validate through reviews.
• Analyze and optimize designs for power, performance, and area.
• Participate in design specification reviews and code reviews.
• Perform lint, CDC, and timing analysis to ensure high-quality implementation.
• Collaborate with verification engineers to validate IP throughout the lifecycle.

Skills

digital logic design

computer architecture

communication skills

problem solving

Education

Bachelor’s or Master’s degree in computer engineering

Tools

Verilog

SystemVerilog

Python

Perl

Tcl

EDA tools

Job description

AMD is seeking an RTL Design Engineer to join the Memory Controller Design team in Austin, TX. You will contribute to IP microarchitecture features and RTL implementations, working closely with architects and verification engineers to deliver high-quality designs for advanced memory technologies.

You should have strong digital logic design experience, proficiency in Verilog/SystemVerilog, and comfort with Python/Perl/Tcl scripting for flows and automation.