Manager of ATE Test Engineering

Astera Labs; San Jose (CA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Flexible time off in the US

Parental leave

401K

Retirement and pension plans

Competitive medical, dental and vision

Job summary

Astera Labs seeks a Manager, ATE Test Engineering in San Jose to lead a growing test organization. You will shape test strategy and guide cross-functional execution as products move from silicon bring-up to high-volume manufacturing.

You will partner with design, DFT, operations, and manufacturing to scale test coverage, quality, and efficiency, influencing product quality and customer readiness in AI infrastructure connectivity.

Qualifications

• Bachelor’s degree in electrical engineering or related field.
• 3+ years of managerial experience building and leading Test engineering teams.
• Experience with PCIe, Ethernet, DDR, NVMe, or USB protocols is required.
• Experience with ATE program development and silicon bring-up.
• Experience leading wafer-sort and final-test hardware development.
• Strong knowledge of DFT techniques: SCAN, MBIST, SerDes, and functional test.
• Proficiency in Python or C/C++ for ATE programming.

Responsibilities

• Lead a high-performing ATE Test engineering team and own a diverse product portfolio.
• Define end-to-end ATE test strategies from design engagement to high-volume production.
• Drive coverage, quality, test time, and cost improvements across lifecycles.
• Oversee silicon and ATE bring-up, bench-to-ATE correlation, and production release.
• Guide tester platform selection and development of load boards and interfaces.
• Collaborate with design, DFT, operations, and manufacturing for readiness.

Skills

ATE Test Engineering

Team Leadership

Test Strategy

DFT (SCAN, MBIST, SerDes)

Python/C++ for ATE

Education

Bachelor’s degree in Electrical Engineering

Master’s or PhD in Electrical Engineering

Tools

Advantest 93k

Teradyne platforms

Python

C/C++

Job description

• Astera Labs is seeking a Manager, ATE Test Engineering to lead our Test engineering organization in San Jose, CA


• This is a critical leadership role responsible for driving next-generation high-speed, high-performance products from silicon bring-up through high-volume manufacturing in advanced process nodes


• Astera Labs is looking to build and scale the Test Engineering team responsible for developing scalable ATE solutions for complex mixed-signal silicon products and high-speed products that power next-generation AI infrastructure


• You will shape test strategy, guide execution across wafer sort and final test, and ensure products move confidently from design through silicon bring-up and high-volume production


• This is an opportunity to combine technical depth with engineering leadership at a hyper-growth connectivity company. Your decisions will directly influence product quality, manufacturing readiness, and customer experience


• You will partner across design, DFT, product engineering, operations, and manufacturing to improve coverage, quality, cost, and test time as Astera Labs scales purpose-built connectivity for rack-scale AI systems


• Team Leadership & Organization Building:


• Build, mentor, and lead a high-performing team of ATE Test engineers owning a diverse portfolio of connectivity products purpose-built for AI infrastructure


• Establish scalable processes, best-known methods (BKMs), and operational excellence frameworks as the organization grows


• Make sound technical and organizational decisions in a fast-paced, dynamic environment with competing priorities


• Test Strategy and Product Ownership:


• Define end-to-end ATE test strategies and plans for high-speed connectivity products from design engagement through high-volume production


• Establish coverage, quality, test-time, cost, and yield objectives, and drive measurable improvements across the product lifecycle


• Lead silicon and ATE bring-up, bench-to-ATE correlation, production release, and ongoing test optimization


• ATE Hardware, Software, and Silicon Validation:


• Guide to tester platform selection and development of load boards, interface hardware, and test solutions for wafer sort and final test


• Direct ATE program development, pattern implementation, debug, and resource optimization on Advantest 93k or Teradyne platforms


• Drive characterization and production test of high-speed SerDes and mixed-signal interfaces, including PCIe, Ethernet, DDR, NVMe, and USB


• Partner with DFT and design teams to implement SCAN, MBIST, SerDes, and functional test methods that maximize defect and parametric coverage


• Cross-Functional Leadership and Manufacturing Execution:


• Build alignment with design, DFT, product engineering, operations, and external manufacturing partners on readiness, risk, and release decisions


• Develop technical talent, set priorities, and create a culture of ownership, rigorous execution, and continuous improvement


• Use data from production, lab equipment, protocol analyzers, oscilloscopes, and manufacturing systems to resolve issues and improve product quality

Benefits

• Flexible time off in the US


• Parental leave


• 401K


• Retirement and pension plans


• Competitive medical, dental and vision plans

Bachelor’s degree in electrical engineering or related technical field3+ years of managerial experience building and leading Test engineering teamAbility to communicate clearly, manage competing priorities, and partner effectively across technical and manufacturing organizationsWorking knowledge of high-speed protocols and physical-layer behavior, including PCIe, Ethernet, DDR, NVMe, or USB8+ years of experience developing and supporting ATE test solutions for complex High-speed products or SoC productsExperience with ATE program development, silicon bring-up, bench-to-ATE correlation, production debug, and test-time optimizationMaster’s or PhD in Electrical Engineering or related fieldExperience leading wafer-sort and final-test hardware development, including high-speed load-board designStrong knowledge of DFT techniques such as SCAN, MBIST, SerDes, and functional test, plus control interfaces including I2C, I3C, SPI, MDIO, and JTAGExperience testing high-speed SerDes operating at 16 Gbps or higher, including external loopback at wafer sortProficiency in C/C++ or Python for ATE programming, data processing, and automation; familiarity with modern databases and RF testing on ATE platformsDemonstrated ability to develop engineers, influence cross-functional decisions, and deliver results in a fast-paced, high-growth environment