Manager, ATE Test Engineering

Astera Labs; San Jose (CA); On-site; USD 195,000 - 250,000; Full time

Job summary

Astera Labs is seeking a Manager, ATE Test Engineering in San Jose, CA to lead the test organization and drive high‑speed connectivity products from silicon bring‑up through high‑volume manufacturing. You will shape strategy, guide wafer sort and final test, and partner across design, DFT, product engineering, operations, and manufacturing to improve coverage, quality, and test time.

This leadership role emphasizes building scalable ATE platforms, reducing cost, and delivering reliable test

Qualifications

• 8+ years in ATE test development for high-speed products
• 3+ years in managerial roles leading Test engineering teams
• Experience with PCIe, Ethernet, DDR, NVMe, USB and related interfaces

Responsibilities

• Lead a team of ATE Test engineers for diverse AI infrastructure connectivity products
• Define end-to-end ATE test strategies from design engagement to high-volume production
• Drive coverage, quality, test time, cost, and yield objectives
• Collaborate with DFT, design, operations, and manufacturing to ensure readiness and release decisions

Skills

Team Leadership

ATE Testing

Cross-functional Collaboration

High-speed Protocols

Test Strategy

Education

Bachelor's in Electrical Engineering

Master's degree preferred

Tools

Advantest 93k

Teradyne

Job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Role Overview

Astera Labs is seeking a Manager, ATE Test Engineering to lead our Test engineering organization in San Jose, CA. This is a critical leadership role responsible for driving next‑generation high-speed, high-performance products from silicon bring‑up through high-volume manufacturing in advanced process nodes.

Astera Labs is looking to build and scale the Test Engineering team responsible for developing scalable ATE solutions for complex mixed-signal silicon products and high-speed products that power next‑generation AI infrastructure. You will shape test strategy, guide execution across wafer sort and final test, and ensure products move confidently from design through silicon bring‑up and high-volume production.

This is an opportunity to combine technical depth with engineering leadership at a hyper‑growth connectivity company. Your decisions will directly influence product quality, manufacturing readiness, and customer experience. You will partner across design, DFT, product engineering, operations, and manufacturing to improve coverage, quality, cost, and test time as Astera Labs scales purpose‑built connectivity for rack‑scale AI systems.

Key Responsibilities

• Team Leadership & Organization Building
  • Build, mentor, and lead a high‑performing team of ATE Test engineers owning a diverse portfolio of connectivity products purpose‑built for AI infrastructure
  • Establish scalable processes, best‑known methods (BKMs), and operational excellence frameworks as the organization grows
  • Make sound technical and organizational decisions in a fast‑paced, dynamic environment with competing priorities

• Test Strategy and Product Ownership
  • Define end‑to‑end ATE test strategies and plans for high‑speed connectivity products from design engagement through high‑volume production.
  • Establish coverage, quality, test‑time, cost, and yield objectives, and drive measurable improvements across the product lifecycle.
  • Lead silicon and ATE bring‑up, bench‑to‑ATE correlation, production release, and ongoing test optimization.

• ATE Hardware, Software, and Silicon Validation
  • Guide to tester platform selection and development of load boards, interface hardware, and test solutions for wafer sort and final test.
  • Direct ATE program development, pattern implementation, debug, and resource optimization on Advantest 93k or Teradyne platforms.
  • Drive characterization and production test of high‑speed SerDes and mixed‑signal interfaces, including PCIe, Ethernet, DDR, NVMe, and USB.
  • Partner with DFT and design teams to implement SCAN, MBIST, SerDes, and functional test methods that maximize defect and parametric coverage.

• Cross-Functional Leadership and Manufacturing Execution
  • Build alignment with design, DFT, product engineering, operations, and external manufacturing partners on readiness, risk, and release decisions.
  • Develop technical talent, set priorities, and create a culture of ownership, rigorous execution, and continuous improvement.
  • Use data from production, lab equipment, protocol analyzers, oscilloscopes, and manufacturing systems to resolve issues and improve product quality.

Basic Qualifications

• Bachelor's degree in electrical engineering or related technical field.
• 8+ years of experience developing and supporting ATE test solutions for complex High-speed products or SoC products.
• 3+ years of managerial experience building and leading Test engineering team
• Working knowledge of high-speed protocols and physical-layer behavior, including PCIe, Ethernet, DDR, NVMe, or USB.
• Experience with ATE program development, silicon bring‑up, bench‑to‑ATE correlation, production debug, and test‑time optimization.
• Ability to communicate clearly, manage competing priorities, and partner effectively across technical and manufacturing organizations.

Preferred Qualifications

• Master’s or PhD in Electrical Engineering or related field.
• Experience leading wafer-sort and final-test hardware development, including high-speed load-board design.
• Strong knowledge of DFT techniques such as SCAN, MBIST, SerDes, and functional test, plus control interfaces including I2C, I3C, SPI, MDIO, and JTAG.
• Experience testing high-speed SerDes operating at 16 Gbps or higher, including external loopback at wafer sort.
• Proficiency in C/C++ or Python for ATE programming, data processing, and automation; familiarity with modern databases and RF testing on ATE platforms.
• Demonstrated ability to develop engineers, influence cross-functional decisions, and deliver results in a fast‑paced, high-growth environment.

Salary range is $195,000 to $250,000 depending on experience, level, and business need. This role may be eligible for discretionary bonuses, incentives and benefits.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.