ATE Test Engineering Manager — High-Speed Silicon Bring-Up

Astera Labs; San Jose (CA); On-site; USD 195,000 - 250,000; Full time

Job summary

Astera Labs is seeking a Manager, ATE Test Engineering in San Jose, CA to lead the test organization and drive high‑speed connectivity products from silicon bring‑up through high‑volume manufacturing. You will shape strategy, guide wafer sort and final test, and partner across design, DFT, product engineering, operations, and manufacturing to improve coverage, quality, and test time.

This leadership role emphasizes building scalable ATE platforms, reducing cost, and delivering reliable test

Qualifications

• 8+ years in ATE test development for high-speed products
• 3+ years in managerial roles leading Test engineering teams
• Experience with PCIe, Ethernet, DDR, NVMe, USB and related interfaces

Responsibilities

• Lead a team of ATE Test engineers for diverse AI infrastructure connectivity products
• Define end-to-end ATE test strategies from design engagement to high-volume production
• Drive coverage, quality, test time, cost, and yield objectives
• Collaborate with DFT, design, operations, and manufacturing to ensure readiness and release decisions

Skills

Team Leadership

ATE Testing

Cross-functional Collaboration

High-speed Protocols

Test Strategy

Education

Bachelor's in Electrical Engineering

Master's degree preferred

Tools

Advantest 93k

Teradyne

Job description

Astera Labs is seeking a Manager, ATE Test Engineering in San Jose, CA to lead the test organization and drive high‑speed connectivity products from silicon bring‑up through high‑volume manufacturing. You will shape strategy, guide wafer sort and final test, and partner across design, DFT, product engineering, operations, and manufacturing to improve coverage, quality, and test time.

This leadership role emphasizes building scalable ATE platforms, reducing cost, and delivering reliable test