ATE Test Engineering Manager – High-Speed AI Infrastructure

Asteralabs; San Jose (CA); On-site; USD 195,000 - 250,000; Full time

Job summary

Astera Labs in San Jose, CA seeks a Manager, ATE Test Engineering to lead the Test engineering organization, driving silicon bring-up through high-volume manufacturing in advanced nodes. You will shape test strategy, oversee wafer sort and final test, and collaborate across design, DFT, product engineering, operations and manufacturing to scale AI connectivity products.

The role emphasizes building teams, improving coverage, cost, and test time, with experience on Advantest 93k or Teradyne

Qualifications

• Bachelor's degree in electrical engineering or related technical field.
• 8+ years of experience developing and supporting ATE test solutions for complex High-speed products or SoC products.
• 3+ years of managerial experience building and leading Test engineering team.
• Working knowledge of high-speed protocols and physical-layer behavior, including PCIe, Ethernet, DDR, NVMe, or USB.
• Experience with ATE program development, silicon bring-up, bench-to-ATE correlation, production debug, and test-time optimization.
• Ability to communicate clearly, manage competing priorities, and partner effectively across technical and manufacturing organizations.

Responsibilities

• Build, mentor, and lead a high-performing team of ATE Test engineers owning a diverse portfolio of connectivity products for AI infrastructure.
• Establish scalable processes, BKMs, and operational excellence frameworks as the organization grows.
• Define end-to-end ATE test strategies and plans for high-speed connectivity products from design engagement through high-volume production.
• Lead silicon and ATE bring-up, bench-to-ATE correlation, production release, and ongoing test optimization.
• Guide tester platform selection and development of load boards, interface hardware, and test solutions for wafer sort and final test.
• Drive characterization and production test of high-speed SerDes and mixed-signal interfaces, including PCIe, Ethernet, DDR, NVMe, and USB.
• Partner with DFT and design teams to implement SCAN, MBIST, SerDes, and functional test methods to maximize defect coverage.

Skills

ATE testing

Team leadership

High-speed protocols

DFT techniques

C/C++ or Python

Education

Bachelor's in Electrical Engineering

Master's or PhD (preferred)

Tools

Advantest 93k

Teradyne platforms

Load boards design

Job description

Astera Labs in San Jose, CA seeks a Manager, ATE Test Engineering to lead the Test engineering organization, driving silicon bring-up through high-volume manufacturing in advanced nodes. You will shape test strategy, oversee wafer sort and final test, and collaborate across design, DFT, product engineering, operations and manufacturing to scale AI connectivity products.

The role emphasizes building teams, improving coverage, cost, and test time, with experience on Advantest 93k or Teradyne