Senior ATE Test Engineer

Astera Labs; San Jose (CA); On-site; USD 136,000 - 170,000; Full time

Benefits offered by this job

Discretionary bonus

Benefits

Job summary

Astera Labs in San Jose, California, seeks a Senior ATE Test Engineer to lead complex mixed-signal SoC test strategies from design through high-volume ramp. You will develop and oversee ATE programs, interact with manufacturing partners, and own testing efforts across wafer sort and final test.

The role requires hands-on experience with high-speed protocols, ATE platforms, and FPGA/embedded scripting, with a focus on quality and manufacturability in a fast-growing AI connectivity company.

Qualifications

• Bachelor's degree in Electrical Engineering required; Master's preferred.
• ≥2 years releasing complex SoC/silicon to high volume manufacturing.
• Experience with high-speed protocols (PCIe, Ethernet, Infiniband, DDR, NVMe, USB).
• Able to multitask with minimal supervision and work in a team.
• Strong communication skills and proactive, can-do attitude.

Responsibilities

• Develop and own the SoC ATE test strategy and programs.
• Collaborate with design and manufacturing to optimize test coverage.
• Select and develop ATE hardware for wafer sort and final test.
• Improve tester resources and reduce ATE test time while preserving quality.
• Implement DFT techniques (SCAN, MEMBIST, SerDes) for coverage.

Skills

Electrical engineering

High-speed protocols

PCIe

Ethernet

Infiniband

DDR

NVMe

USB

Team collaboration

Programming (C/C++, Python)

Education

Bachelor's in EE

Master's preferred

Tools

Advantest 93k ATE

Oscilloscopes

Protocol analyzers

Bench-ATE

I2C/I3C/SPI/JTAG

Job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com .

Role Overview

We are looking for Senior ATE Test Engineerswith proven experience in developing and supporting complex mixed-signal silicon SoC products to lead ATE Test solutions. The ideal candidate will develop and oversee SoC test strategy, interact with manufacturing partners, define, and implement ATE programs and own the product from design, initial samples all the way through high volume production ramp. The candidate should have working knowledge of communication/interface protocols such as PCI-Express (Gen-4/5/6), Ethernet, Infiniband, DDR, NVMe, USB, etc. This is an opportunity to contribute hands‑on technical expertise within Astera Labs’ hyper‑growth connectivity business and help deliver purpose‑built solutions that scale with the demands of rack‑scale AI systems.

Basic Qualifications

• Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, and a Master’s is preferred.
• ≥2 year experience releasing complex SoC/silicon products to high volume manufacturing.
• Working knowledge of high-speed protocols like PCIe, Ethernet, Infiniband, DDR, NVMe, USB, etc.
• Professional attitude with ability to execute on multiple tasks with minimal supervision.
• Strong team player with good communication skills to work alongside a team of high caliber engineers.
• Entrepreneurial, open-mind behavior and can-do attitude.

Required Experience

• Hands-on experience with high-speed mixed signal SoC test program/hardware development on multiple high-speed test platforms.
• Collaboration with design team to define test strategy, create and own test plan.
• Tester platform selection, design, and development of ATE hardware for wafer sort and final test.
• Familiar with high-speed load board design techniques.
• Proven track record of implementing ATE patterns to optimize tester resources and minimize ATE test time while maintaining product quality.
• Strong knowledge and development of DFT techniques implemented in silicon that provide maximum defect and parametric device coverage – SCAN, MEMBIST, SerDes and other functional tests.
• Skilled in control interfaces – I2C, I3C, SPI, MDIO, JTAG etc.Li>
• Expertise in production test of high speed SerDes operating at 16Gbps and higher.
• Skilled in ATE programming, silicon/ATE bring-up, bench-ATE correlation and debug.
• Experience with lab equipment including protocol analyzers and oscilloscopes.
• Experience with using Advantest 93k ATE platform.
• Proficiency in, at least, one modern programming language such as C/C++, Python.

Preferred Experience

• Fluent in data processing using high level programming languages.
• Experience in running External loopback at wafer sort.
• Familiarity with modern databases

Salary range is $135,500 to $170,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

This role requires in-person presence in San Jose, CA.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.