Senior ATE Test Engineer - SoC & High-Speed Protocols

Astera Labs; San Jose (CA); Hybrid; USD 136,000 - 170,000; Full time

Job summary

Astera Labs in San Jose, CA is seeking Senior ATE Test Engineers to lead ATE test solutions for complex mixed‑signal SoC products, spanning from design and initial samples to high‑volume production ramp.

You will work with manufacturing partners to define and implement ATE programs, own test strategy, and ensure robust production test. Strong expertise in high‑speed protocols and ATE tooling is required for this role.

Qualifications

• Hands-on experience with high-speed mixed-signal SoC test programs.
• Collaboration with design teams to define test strategy and test plans.
• ATE hardware for wafer sort and final test development.
• Familiar with high-speed load board design techniques.

Responsibilities

• Lead ATE test solutions for complex mixed-signal SoCs.
• Develop and own test strategy from design to high-volume ramp.
• Interact with manufacturing partners to implement programs.
• Optimize tester resources and maximize coverage with DFT.

Skills

PCIe

Ethernet

Infiniband

DDR

NVMe

USB

C/C++

Python

DFT techniques

Oscilloscopes

Protocol analyzers

Advantest 93k

Education

Bachelor’s in Electrical Engineering

Master’s in Electrical Engineering

Tools

Advantest 93k ATE

Job description

Astera Labs in San Jose, CA is seeking Senior ATE Test Engineers to lead ATE test solutions for complex mixed‑signal SoC products, spanning from design and initial samples to high‑volume production ramp.

You will work with manufacturing partners to define and implement ATE programs, own test strategy, and ensure robust production test. Strong expertise in high‑speed protocols and ATE tooling is required for this role.