Low-Power Verification Engineer, Physical Design (TPU)

Google LLC; Sunnyvale (CA); On-site; USD 163,000 - 236,000; Full time

Job summary

Google LLC in Sunnyvale, CA is seeking a Low Power Verification Engineer for Physical Design. You will verify low-power integrity in post-layout netlists, run UPF checks, and debug power/ground issues across synthesis to place and route.

The role emphasizes creating scalable verification workflows, automating ECOs with Tcl/Python, and collaborating with P&R teams to ensure robust multi-voltage designs for TPU-powered AI hardware.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
• 8 years of post-layout physical netlist validation and low-power signoff experience.
• Experience with static low-power rule-checking tools (VCLP/CLP) and debugging failures.
• Experience validating isolation cells, power switches, level shifters, retention registers, and always-on cells.

Responsibilities

• Design, deploy, and run post-layout low-power verification to meet tapeout signoff criteria.
• Validate multi-voltage design collateral with gate-level checks for UPF alignment.
• Resolve physical design and Place & Route anomalies affecting power delivery and timing.
• Debug CTS implementations and level shifters in high fanout networks.
• Refine PST and UPF scripts to map RTL to the final netlist.

Skills

Low-power verification

Post-layout verification

Power integrity debugging

Education

Bachelor's degree in EE/CE or equivalent

Master's or PhD in EE/CE/CS (computer architecture focus)

Tools

Synopsys VCLP

Innovus

Fusion

Tcl

Python

Job description

Google LLC in Sunnyvale, CA is seeking a Low Power Verification Engineer for Physical Design. You will verify low-power integrity in post-layout netlists, run UPF checks, and debug power/ground issues across synthesis to place and route.

The role emphasizes creating scalable verification workflows, automating ECOs with Tcl/Python, and collaborating with P&R teams to ensure robust multi-voltage designs for TPU-powered AI hardware.