Senior Low-Power Verification Engineer — Physical Design

Google; Sunnyvale (CA); On-site; USD 163,000 - 236,000; Full time

Benefits offered by this job

Equity

Bonus target

Benefits

Job summary

Google in Sunnyvale, CA seeks a senior ASIC verification engineer focused on post-layout low-power signoff and TPU architecture to shape AI/ML hardware acceleration.

You will validate UPF, work with Synopsys VCLP, Innovus and Fusion, and drive multi-Voltage design signoff from synthesis to place and route.

The role offers equity and a 15% target bonus, with opportunities to impact Google's next generation TPU systems.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
• 8 years of experience in post-layout physical netlist validation and low-power signoff in advanced ASIC design workflows.
• Experience with static low-power rule-checking tools (VCLP/CLP) and debugging structural checks and signal corruption issues.
• Experience validating isolation cells, power switches, level shifters, retention registers, and always-on cells across synthesis to place-and-route.

Responsibilities

• Design, deploy, and carry out post-layout low power verification methodologies per tapeout signoff criteria.
• Validate multi-voltage design collateral with gate-level checks to ensure power/ground integrity and UPF alignment.
• Drive resolution of Physical Design and Place & Route anomalies, mitigating wrong-domain buffering and isolation issues.
• Debug CTS implementations, analyze level shifter behavior and high-fanout networks, and manage multi-voltage skew.
• Refine power state tables and UPF scripts to translate Golden RTL to final physical netlist.

Skills

Post-layout verification

Low-power signoff

Debugging checks

Power integrity issues

Education

Bachelor's degree in Electrical/Computer Engineering or equivalent

Tools

Synopsys VCLP

Innovus

Fusion

Job description

Google in Sunnyvale, CA seeks a senior ASIC verification engineer focused on post-layout low-power signoff and TPU architecture to shape AI/ML hardware acceleration.

You will validate UPF, work with Synopsys VCLP, Innovus and Fusion, and drive multi-Voltage design signoff from synthesis to place and route.

The role offers equity and a 15% target bonus, with opportunities to impact Google's next generation TPU systems.