Lead Verification Engineer - Memory Interconnect (Hybrid)

OSI Engineering; United States; Hybrid; USD 170,000 - 196,000; Full time

Job summary

A leading chip and silicon IP provider is looking for a Principal Verification Engineer to work in a hybrid role. This position involves leading verification efforts, implementing testbenches, and ensuring quality. Ideal candidates will have significant experience in System Verilog and UVM methodology with a strong educational background in Electrical Engineering. Join a team that values collaboration and innovation while working on advanced technologies in attractive locations such as San Jose, CA, and Morrisville, NC.

Qualifications

• 10+ years of verification experience with MS in Electrical Engineering.
• 7+ years of verification experience with PhD in Electrical Engineering.
• Experience with verification of DDR memory interfaces is desirable.

Responsibilities

• Lead full-chip and block-level verification efforts.
• Define and implement verification plans and testbenches.
• Support silicon bring-up, lab testing, and debugging.

Skills

System Verilog

UVM methodology

Linux/Unix scripting

Complex technical solutions

Education

MS in Electrical Engineering

PhD in Electrical Engineering

Tools

Synopsys VCS

Cadence Xcelium

Cadence IMC

Jenkins

Job description

A leading chip and silicon IP provider is looking for a Principal Verification Engineer to work in a hybrid role. This position involves leading verification efforts, implementing testbenches, and ensuring quality. Ideal candidates will have significant experience in System Verilog and UVM methodology with a strong educational background in Electrical Engineering. Join a team that values collaboration and innovation while working on advanced technologies in attractive locations such as San Jose, CA, and Morrisville, NC.