Hybrid Principal Verification Engineer — Lead Full-Chip UVM

OSI Engineering; San Jose (CA); Hybrid; USD 170,000 - 196,000; Full time

Job summary

A leading chip and silicon IP provider is seeking a Principal Verification Engineer in San Jose, CA. This full-time hybrid role involves leading verification strategies and working alongside talented engineers. Candidates should have extensive experience in SystemVerilog and UVM, with a strong background in ASIC verification tools. The position offers a salary range of $170,000 – $196,000 based on experience.

Qualifications

• 10+ years of verification experience with MS or 7+ years with PhD in EE.
• Demonstrated ability to lead and drive technical solutions.
• Strong commitment to cross-functional teamwork.

Responsibilities

• Lead verification for full-chip and block-level designs.
• Define verification plans with architects and designers.
• Implement testbenches and achieve quality goals.

Skills

SystemVerilog proficiency

UVM experience

Experience with ASIC verification flow

Simulation tools expertise

Scripting in Linux/Unix

Education

MS in Electrical Engineering

PhD in Electrical Engineering

Tools

Synopsys VCS

Cadence Xcelium

Cadence IMC

Jenkins

Job description

A leading chip and silicon IP provider is seeking a Principal Verification Engineer in San Jose, CA. This full-time hybrid role involves leading verification strategies and working alongside talented engineers. Candidates should have extensive experience in SystemVerilog and UVM, with a strong background in ASIC verification tools. The position offers a salary range of $170,000 – $196,000 based on experience.