Principal Verification Engineer

OSI Engineering; San Jose (CA); Hybrid; USD 170,000 - 196,000; Full time

Job summary

A leading chip and silicon IP provider is seeking a Principal Verification Engineer in San Jose, CA. This full-time hybrid role involves leading verification strategies and working alongside talented engineers. Candidates should have extensive experience in SystemVerilog and UVM, with a strong background in ASIC verification tools. The position offers a salary range of $170,000 – $196,000 based on experience.

Qualifications

• 10+ years of verification experience with MS or 7+ years with PhD in EE.
• Demonstrated ability to lead and drive technical solutions.
• Strong commitment to cross-functional teamwork.

Responsibilities

• Lead verification for full-chip and block-level designs.
• Define verification plans with architects and designers.
• Implement testbenches and achieve quality goals.

Skills

SystemVerilog proficiency

UVM experience

Experience with ASIC verification flow

Simulation tools expertise

Scripting in Linux/Unix

Education

MS in Electrical Engineering

PhD in Electrical Engineering

Tools

Synopsys VCS

Cadence Xcelium

Cadence IMC

Jenkins

Job description

Principal Verification Engineer – OSI Engineering

A leading chip and silicon IP provider is seeking a talented Principal Verification Engineer to join its Memory Interconnect Design team. In this full‑time hybrid role you will work alongside world‑class engineers to develop advanced technologies that make data faster and more secure.

As a key technical leader, you will define and execute verification strategies across multiple product lines and global sites, ensuring robust, production‑ready silicon.

Responsibilities

• Technical lead for full‑chip and block‑level verification
• Define verification plans in coordination with architects, logic, and mixed‑signal designers
• Implement testbenches, monitors, and scoreboards using UVM methodology
• Achieve functional and code coverage goals to ensure quality and completeness
• Support silicon bring‑up, lab testing, and debug in partnership with the system team
• Contribute to the development of verification flows, tools, and methodology
• Mentor and guide junior engineers within the team

Requirements

• Proficient in SystemVerilog or Verilog with significant UVM experience
• Strong experience with standard ASIC verification flow/software tools
• Simulation tools: Synopsys VCS, Cadence Xcelium
• Coverage & Analysis: Cadence IMC (Incisive Metrics Center)
• Experience scripting in Linux/Unix environments
• Desirable: verification of DDR memory interfaces
• Desirable: experience with analog/mixed‑signal products
• Desirable: SVA (System/Verilog Assertions)
• Desirable: Jenkins (CI/CD integration)
• Demonstrated ability to lead and drive complex technical solutions
• Strong commitment to work in cross‑functional and globally dispersed teams
• MS in EE with 10+ years, OR PhD in EE with 7+ years of verification experience

Location

San Jose, CA; Agoura Hills, CA; Morrisville, NC; Johns Creek, GA (hybrid)

Employment Type

Full‑time

Salary Range

$170,000 – $196,000 (DOE)

Additional Information

No 3rd party agencies or C2C